Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10636795-B2
Application number	US-201916412870-A
Country	US
Kind code	B2
Filing date	May 15, 2019
Priority date	Jun 2, 2016
Publication date	Apr 28, 2020
Grant date	Apr 28, 2020

Abstract

A semiconductor device includes a lower electrode on a substrate, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor dielectric layer. The capacitor dielectric layer includes a base layer on the lower electrode and a dielectric particle layer in at least a portion of the base layer. The base layer includes a first dielectric material, and the dielectric particle layer extends at least partially continuously along a thickness direction of the capacitor dielectric layer and includes a second dielectric material different from the first dielectric material.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate;
a gate structure disposed in a trench in the substrate, the gate structure extending in a first direction parallel to a top surface of the substrate;
a bit line structure on the substrate, the bit line structure extending in a second direction different from the first direction;
a capacitor contact on the substrate; and
a capacitor structure on the capacitor contact, the capacitor structure including:
a lower electrode on the capacitor contact;
a capacitor dielectric layer on a top surface of the lower electrode; and
an upper electrode on the capacitor dielectric layer,

wherein the capacitor dielectric layer comprises:
a base layer comprising a first dielectric material; and
a plurality of dielectric nanoparticles dispersed in the base layer, each of the plurality of dielectric nanoparticles comprising a second dielectric material which is different from the first dielectric material, wherein a first density of dielectric nanoparticles dispersed in a first portion of the base layer is higher than a second density of dielectric nanoparticles dispersed in a second portion of the base layer, wherein the second portion of the base layer is closer to the top surface of the lower electrode than the first portion of the base layer.

2. The semiconductor device of claim 1 , wherein a third portion of the base layer is substantially free of the dielectric nanoparticles, and the third portion of the base layer is closer to the top surface of the lower electrode than the second portion of the base layer.

3. The semiconductor device of claim 1 , wherein the base layer includes crystal grains, and the plurality of dielectric nanoparticles fill at least a portion of grain boundary space formed between the crystal grains.

4. The semiconductor device of claim 3 , wherein each of the dielectric nanoparticles has a diameter of about 1 Å to 10 Å and a thickness of the capacitor dielectric layer is about 20 Angstroms (Å) to 80 Å.

5. The semiconductor device of claim 1 , wherein the first dielectric material comprises a metal oxide having a dielectric constant of about 4 to about 40, and the second dielectric material comprises one or more material of Al 2 O 3 , BeO, B 2 O 3 , SiO 2 , Sc 2 O 3 , Y 2 O 3 , La 2 O 3 , AlN, BN and Si 3 N 4 .

6. The semiconductor device of claim 1 , further comprising a dielectric capping layer conformally disposed between the base layer and the upper electrode, the dielectric capping layer comprising the second dielectric material.

7. The semiconductor device of claim 1 , wherein the base layer comprises a first base layer and a second base layer which are vertically stacked, and are formed through separate process steps, wherein a bottom surface of the second base layer is in contact with a top surface of the first base layer.

8. The semiconductor device of claim 7 , wherein grain boundaries of crystal grains have discontinuities at an interface between the first base layer and the second base layer, and the dielectric nanoparticles are disposed at the grain boundaries at an interface between the first base layer and the second base layer.

9. A semiconductor device comprising:
a substrate; and
a capacitor structure on the substrate, the capacitor structure comprising:
a lower electrode on the substrate;
a capacitor dielectric layer on the lower electrode; and
an upper electrode on the capacitor dielectric layer,

wherein the capacitor dielectric layer comprises:
a first base layer on a top surface of the lower electrode, the first base layer comprising a first dielectric material;
a second base layer on the first base layer, the second base layer comprising the first dielectric material; and
a plurality of dielectric nanoparticles dispersed in the first base layer and the second base layer, each of the plurality of dielectric nanoparticles comprising a second dielectric material different from the first dielectric material, wherein a first density of dielectric nanoparticles dispersed in the first base layer is lower than a second density of dielectric nanoparticles dispersed in the second base layer, wherein a third density of dielectric nanoparticles dispersed in an upper portion of the first base layer is greater than a fourth density of dielectric nanoparticles dispersed in a lower portion of the first base layer.

10. The semiconductor device of claim 9 , wherein the first base layer and the second base layer include crystal grains respectively, and the plurality of dielectric nanoparticles fill at least a portion of grain boundary space formed between the crystal grains, and the dielectric nanoparticles are disposed at grain boundaries of the crystal grains between the first base layer and the second base layer,
wherein the plurality of dielectric nanoparticles having a dot shape are randomly dispersed at the grain boundary space.

11. The semiconductor device of claim 9 , wherein the lower portion of the first base layer is substantially free of the dielectric nanoparticles.

12. The semiconductor device of claim 9 , wherein the second dielectric material comprises a material having a band gap energy higher than a band gap energy of the first dielectric material.

13. The semiconductor device of claim 9 , wherein the second dielectric material comprises a material having a dielectric constant smaller than a dielectric constant of the first dielectric material.

14. The semiconductor device of claim 9 , further comprising:
a gate structure disposed in a trench in the substrate, the gate structure extending in a first direction parallel to a top surface of the substrate; and
a bit line structure on the substrate, the bit line structure extending in a second direction different from the first direction,
wherein the capacitor structure is disposed at a level higher than the bit line structure.

15. The semiconductor device of claim 14 , wherein the lower electrode has a cylindrical shape extending in a third direction perpendicular to the top surface of the substrate, and
the capacitor dielectric layer is disposed conformally on the top surface and a sidewall of the lower electrode.

16. The semiconductor device of claim 14 , wherein the lower electrode has a pillar shape extending in a third direction perpendicular to the top surface of the substrate, and
the capacitor dielectric layer is disposed conformally on the top surface and a sidewall of the lower electrode.

17. A semiconductor device comprising:
a substrate;
a gate structure disposed in a trench in the substrate, the gate structure extending in a first direction parallel to a top surface of the substrate;
a bit line structure on the substrate, the bit line structure extending in a second direction different from the first direction;
a capacitor contact on the substrate; and
a capacitor structure on the capacitor contact, the capacitor structure comprising:
a lower electrode on the capacitor contact;
a first interface layer on a top surface of the lower electrode;
a capacitor dielectric layer on the first interface layer;
a second interface layer on the capacitor dielectric layer; and
an upper electrode on the second interface layer,

wherein the capacitor dielectric layer comprises:
a first base layer on a top surface of the first interface layer, the first base layer comprising a first dielectric material;
a second base layer directly on the first base layer, the second base layer comprising the first dielectric material, wherein the first base layer and the second base layer include cry

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ahn Se-Hyoung
• Kim Youn-Soo
• Choi Jae-Hyoung
• Chang Jae-Wan
• MOON Sun-min
• Lee Jin-Sun

Classifications

• H01L27/10823

  Electricity · mapped topic

• H01L27/10885

  Electricity · mapped topic

• H01L27/10855

  Electricity · mapped topic

• H01L28/90

  Electricity · mapped topic

• H01L27/10814 Primary

  Electricity · mapped topic