Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10297600-B2
Application number	US-201815956287-A
Country	US
Kind code	B2
Filing date	Apr 18, 2018
Priority date	Jun 2, 2016
Publication date	May 21, 2019
Grant date	May 21, 2019

Abstract

A semiconductor device includes a lower electrode on a substrate, a capacitor dielectric layer on the lower electrode, and an upper electrode on the capacitor dielectric layer. The capacitor dielectric layer includes a base layer on the lower electrode and a dielectric particle layer in at least a portion of the base layer. The base layer includes a first dielectric material, and the dielectric particle layer extends at least partially continuously along a thickness direction of the capacitor dielectric layer and includes a second dielectric material different from the first dielectric material.

First claim

What is claimed is:

1. A capacitor structure for a semiconductor device comprising:
a lower electrode on a substrate;
a capacitor dielectric layer on a top surface of the lower electrode; and
an upper electrode on the capacitor dielectric layer,
wherein the capacitor dielectric layer comprises:
a base layer comprising a first dielectric material; and
a plurality of dielectric nanoparticles dispersed in the base layer, each of the plurality of dielectric nanoparticles comprising a second dielectric material which is different from the first dielectric material, wherein a first density of dielectric nanoparticles dispersed in a first portion of the base layer is higher than a second density of dielectric nanoparticles dispersed in a second portion of the base layer, wherein the second portion of the base layer is closer to the top surface of the lower electrode than the first portion of the base layer, and

wherein a thickness of the capacitor dielectric layer is about 20 Angstroms (Å) to 80 Å.

2. The capacitor structure of claim 1 , wherein the base layer includes crystal grains, and the plurality of dielectric nanoparticles fill at least a portion of grain boundary space formed between the crystal grains.

3. The capacitor structure of claim 2 , wherein each of the dielectric nanoparticles has a diameter of about 1 Å to 10 Å.

4. The capacitor structure of claim 1 , wherein a surface roughness of the capacitor dielectric layer is 0.3 nm or less.

5. A capacitor structure for a semiconductor device comprising:
a lower electrode on a substrate;
a capacitor dielectric layer on a top surface of the lower electrode; and
an upper electrode on the capacitor dielectric layer,
wherein the capacitor dielectric layer comprises:
a base layer comprising a first dielectric material; and
a plurality of dielectric nanoparticles dispersed in the base layer, each of the plurality of dielectric nanoparticles comprising a second dielectric material which is different from the first dielectric material, wherein a first density of dielectric nanoparticles dispersed in a first portion of the base layer is higher than a second density of dielectric nanoparticles dispersed in a second portion of the base layer, wherein the second portion of the base layer is closer to the top surface of the lower electrode than the first portion of the base layer,

wherein the first dielectric material comprises one or more material of zirconium oxide (ZrO 2 ), hafnium oxide (HfO 2 ) , zirconium silicon oxide (ZrSiO x ), hafnium silicon oxide (HfSiO x ), and zirconium hafnium silicon oxide (ZrHfSiO x ).

6. The capacitor structure of claim 1 , wherein the second dielectric material comprises one or more material of Al 2 O 3 , BeO, B 2 O 3 , SiO 2 , Sc 2 O 3 , Y 2 O 3 , La 2 O 3 , AlN, BN and Si 3 N 4 .

7. The capacitor structure of claim 1 , further comprising a dielectric capping layer conformally disposed between the base layer and the upper electrode.

8. The capacitor structure of claim 1 , wherein the base layer comprises a first base layer and a second base layer which are vertically stacked, and are formed through separate process steps.

9. The capacitor structure of claim 8 , wherein grain boundaries of crystal grains have discontinuities at an interface between the first base layer and the second base layer.

10. The capacitor structure of claim 9 , further comprising a dielectric particle layer disposed at the interface between the first base layer and the second base layer, wherein the dielectric particle layer comprises the second dielectric material.

11. A capacitor structure for a semiconductor device comprising:
a lower electrode on a substrate;
a capacitor dielectric layer on the lower electrode; and
an upper electrode on the capacitor dielectric layer,
wherein the capacitor dielectric layer comprises:
a first base layer on a top surface of the lower electrode, the first base layer comprising a first dielectric material;
a second base layer on the first base layer, the second base layer comprising the first dielectric material; and

a plurality of dielectric nanoparticles dispersed in the first base layer and the second base layer, each of the plurality of dielectric nanoparticles comprising a second dielectric material different from the first dielectric material, wherein a first density of dielectric nanoparticles dispersed in the first base layer is lower than a second density of dielectric nanoparticles dispersed in the second base layer.

12. The capacitor structure of claim 11 , wherein a thickness of the capacitor dielectric layer is about 20 Å to 80 Å.

13. The capacitor structure of claim 12 , wherein the first base layer and the second base layer include crystal grains respectively, and the plurality of dielectric nanoparticles fill at least a portion of grain boundary space formed between the crystal grains.

14. The capacitor structure of claim 13 , wherein grain boundaries of the crystal grains have discontinuities at an interface between the first base layer and the second base layer.

15. The capacitor structure of claim 13 , wherein each of the plurality of dielectric nanoparticles has a diameter of about 1 Å to 10 Å.

16. The capacitor structure of claim 11 , wherein a surface roughness of the capacitor dielectric layer is 0.3 nm or less.

17. The capacitor structure of claim 11 , wherein the first dielectric material comprises one or more material of zirconium oxide (ZrO 2 ), hafnium oxide (HfO 2 ), zirconium silicon oxide (ZrSiO x ), hafnium silicon oxide (HfSiO x ), and zirconium hafnium silicon oxide (ZrHfSiO x ).

18. The capacitor structure of claim 11 , wherein the second dielectric material comprises one or more material of Al 2 O 3 , BeO, B 2 O 3 , SiO 2 , Sc 2 O 3 , Y 2 O 3 , La 2 O 3 , AlN, BN and Si 3 N 4 .

19. The capacitor structure of claim 11 , further comprising a dielectric capping layer conformally disposed between the first base layer and the upper electrode.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ahn Se-Hyoung
• Kim Youn-Soo
• Choi Jae-Hyoung
• Chang Jae-Wan
• MOON Sun-min
• Lee Jin-Sun

Classifications

• H01L27/10855

  Electricity · mapped topic

• H01L27/10888

  Electricity · mapped topic

• H01L27/10823

  Electricity · mapped topic

• H01L27/10885

  Electricity · mapped topic

• H01L27/10814 Primary

  Electricity · mapped topic