Method of forming a semiconductor device using layered etching and repairing of damaged portions

Patent metadata

Field	Value
Publication number	US-10636652-B2
Application number	US-201916383560-A
Country	US
Kind code	B2
Filing date	Apr 12, 2019
Priority date	Mar 17, 2017
Publication date	Apr 28, 2020
Grant date	Apr 28, 2020

Abstract

A method of fabricating a semiconductor device includes plasma etching a portion of a plurality of metal dichalcogenide films comprising a compound of a metal and a chalcogen disposed on a substrate by applying a plasma to the plurality of metal dichalcogenide films. After plasma etching, a chalcogen is applied to remaining portions of the plurality of metal dichalcogenide films to repair damage to the remaining portions of the plurality of metal dichalcogenide films from the plasma etching. The chalcogen is S, Se, or Te.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a first metal dichalcogenide monolayer comprising a compound of a first metal and a first chalcogen disposed on a substrate;
a second metal dichalcogenide monolayer comprising a compound of a second metal and a second chalcogen disposed on the first metal dichalcogenide monolayer; and
source and drain electrodes disposed on the first metal dichalcogenide monolayer on opposing sides of the second metal dichalcogenide monolayer,
wherein substantially no oxides of the first metal exist at an interface on top of the first metal dichalcogenide monolayer where the source and drain electrodes are in direct contact with the first metal dichalcogenide monolayer, and wherein the first metal dichalcogenide monolayer is closer to the substrate than the second metal dichalcogenide monolayer.

2. The semiconductor device of claim 1 , wherein the first and second chalcogens are S, Se, or Te.

3. The semiconductor device of claim 2 , wherein the first metal dichalcogenide monolayer and the second metal dichalcogenide monolayer comprise different metal dichalcogenides.

4. The semiconductor device of claim 1 , further comprising a channel region comprising the first and second metal dichalcogenide monolayers between the source and drain electrodes.

5. The semiconductor device of claim 1 , further comprising:
a dielectric layer disposed on the second metal dichalcogenide monolayer and the source and drain electrodes; and
a gate electrode disposed on the dielectric layer vertically aligned with the second metal dichalcogenide monolayer between the source and drain electrodes.

6. The semiconductor device of claim 1 , wherein the first and second metal dichalcogenide monolayers comprise a metal dichalcogenide selected from the group consisting of WS 2 , MoS 2 , WSe 2 , MoSe 2 , WTe 2 , and MoTe 2 .

7. The semiconductor device of claim 1 , wherein the substrate comprises silicon, silicon oxide, or aluminum oxide.

8. The semiconductor device of claim 1 , wherein:
the substrate comprises sapphire,
the first metal dichalcogenide monolayer comprises MoS 2 , MoSe 2 , or MoTe 2 and
the second metal dichalcogenide monolayer comprises WS 2 , WSe 2 , or WTe 2 .

9. A semiconductor device, comprising:
a plurality of metal dichalcogenide films comprising a compound of a metal and a chalcogen disposed on a substrate; and
source and drain electrodes disposed on opposing sides of a first metal dichalcogenide film and in contact with the first metal dichalcogenide film, the first metal dichalcogenide film is a top most metal dichalcogenide film of the plurality of metal dichalcogenide films, and the source and drain electrodes and the first metal dichalcogenide film are disposed on a second metal dichalcogenide film of the plurality of metal dichalcogenide films,
wherein substantially no metal oxides exist at an interface on top of the second metal dichalcogenide film where the source and drain electrodes are in direct contact with the second metal dichalcogenide film, the second metal dichalcogenide film is closer to the substrate than the first metal dichalcogenide film, and substantially no metal oxides exist at an interface between the source and drain electrodes and the first metal dichalcogenide film.

10. The semiconductor device of claim 9 , wherein the plurality of metal dichalcogenide films have a thickness of about 0.5 nm to about 10 nm.

11. The semiconductor device of claim 9 , wherein the chalcogen is sulfur, and wherein metal sulfides exists in the interface between the source and drain electrodes and the first metal dichalcogenide film.

12. The semiconductor device of claim 9 , wherein the chalcogen in the first and second metal dichalcogenide films is S, Se, or Te.

13. The semiconductor device of claim 9 , wherein the first metal dichalcogenide film and the second metal dichalcogenide film comprise different metal dichalcogenides.

14. The semiconductor device of claim 9 , wherein the plurality of metal dichalcogenide films comprise a metal dichalcogenide selected from the group consisting of WS 2 , MoS 2 , WSe 2 , MoSe 2 , WTe 2 , and MoTe 2 .

15. A semiconductor device, comprising:
a plurality of metal dichalcogenide monolayers comprising a first metal dichalcogenide monolayer and a second metal dichalcogenide monolayer disposed on the first metal dichalcogenide monolayer, the first metal dichalcogenide monolayer comprises a compound of a first metal and the second metal dichalcogenide monolayer comprises a compound of a second metal; and
source and drain electrodes disposed on the first metal dichalcogenide monolayer on opposing sides of the second metal dichalcogenide monolayer and in contact with the second metal dichalcogenide monolayer,
wherein substantially no oxides of the first metal exist at an interface on top of the first metal dichalcogenide monolayer where the source and drain electrodes are in direct contact with the first metal dichalcogenide monolayer, the first metal dichalcogenide monolayer is closer to the substrate than the second metal dichalcogenide monolayer, and substantially no oxides of the second metal exist at an interface between the source and drain electrodes and the second metal dichalcogenide monolayer.

16. The semiconductor device of claim 15 , wherein the first metal dichalcogenide monolayer and the second metal dichalcogenide monolayer comprise different metal dichalcogenides.

17. The semiconductor device of claim 15 , further comprises a channel region comprising the first and second metal dichalcogenide monolayers between the source and drain electrodes.

18. The semiconductor device of claim 17 , further comprising:
a dielectric layer disposed on the second metal dichalcogenide monolayer and the source and drain electrodes; and
a gate electrode disposed on the dielectric layer vertically aligned with the second metal dichalcogenide monolayer in the channel region.

19. The semiconductor device of claim 15 , wherein:
the first metal dichalcogenide monolayer comprises MoS 2 , MoSe 2 , or MoTe 2 and the second metal dichalcogenide monolayer comprises WS 2 , WSe 2 , or WTe 2 .

20. The semiconductor device of claim 15 , wherein a chalcogen of the plurality of metal dichalcogenide monolayers is S, Se, or Te.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Univ Nat Taiwan

Inventors

• Lin Shih-Yen
• Chen Kuan-Chao
• Lee Si-Chen
• Pan Samuel C

Classifications

• H10P50/242

  of Group IV materials · CPC title

• H10P14/3246

  Monolayers · CPC title

• H10P14/2921

  being crystalline insulating materials · CPC title

• H10P14/668

  the materials being characterised by the deposition precursor materials · CPC title

• H10P14/203

  using transformation of metal, e.g. oxidation or nitridation · CPC title