Semiconductor memory device error correction circuit, semiconductor memory device including the same, and memory system including the same

Patent metadata

Field	Value
Publication number	US-10635531-B2
Application number	US-201815870220-A
Country	US
Kind code	B2
Filing date	Jan 12, 2018
Priority date	Jul 6, 2017
Publication date	Apr 28, 2020
Grant date	Apr 28, 2020

Abstract

An error correction circuit of a semiconductor memory device including a memory cell array includes an error correction code (ECC) memory that stores an ECC and an ECC engine. The ECC is represented by a generation matrix. The ECC engine generates first parity data based on main data using the ECC, and corrects at least one error bit in the main data read from the memory cell array using the first parity data. The main data includes a plurality of data bits divided into a plurality of sub codeword groups. The ECC includes a plurality of column vectors divided into a plurality of code groups corresponding to the sub codeword groups. The column vectors have elements configured to restrict a location of a sub codeword group in which a mis-corrected bit occurs, in which the mis-corrected bit is generated due to error bits in the main data.

First claim

What is claimed is:

1. An error correction circuit of a semiconductor memory device comprising a memory cell array, wherein the error correction circuit comprises:
an error correction code (ECC) memory that stores an ECC, wherein the ECC is represented by a generation matrix; and
an ECC engine configured to generate first parity data based on main data using the ECC, and to correct at least one error bit in the main data read from the memory cell array using the first parity data, wherein the at least one error bit comprises a first error hit and a second error bit,
wherein the main data includes a plurality of data bits divided into a plurality of sub codeword groups,
wherein the ECC includes a plurality of column vectors divided into a plurality of code groups corresponding to the sub codeword groups,
wherein a first code group corresponding to a first sub codeword group includes a plurality of first column vectors, and a second code group corresponding to a second sub codeword group includes a plurality of second column vectors,
wherein, when the first sub codeword group includes the first error bit and the second sub codeword group includes the second error bit, the first column vectors and the second column vectors are arranged in bit configurations such that a result of a bit-wise exclusive OR operation of each of the first column vectors and each of the second column, vectors matches with one of the column vectors in the code groups other than the first code group and the second code group.

2. The error correction circuit of claim 1 , wherein:
when the first sub codeword group includes the first error bit and the second error bit, the first column vectors are arranged in bit configurations such that a result of the bit-wise exclusive OR operation of two different column vectors of the first column vectors differs from each of the column vectors in the code groups.

3. The error correction circuit of claim 1 , wherein:
the main data includes 2 p -bit of the data bits, wherein p is an integer equal to or greater than seven;
the first parity data includes (p+1)-bit parity bits;
the ECC is a single error correction (SEC) code;
the sub codeword groups include the first sub codeword group, the second sub codeword group, a third sub codeword group, and a fourth sub codeword group, and each of the first through fourth sub codeword groups includes 2 p-2 bits; and
the code groups include be first code group, the second code group, a third code group, and a fourth code group corresponding to the first through fourth sub codeword groups, respectively.

4. The error correction circuit of claim 3 , wherein:
each of the first through fourth code groups includes first through 2 p-2 -th column vectors; and
each of the first through 2 p-2 -th column vectors includes (p+1) elements.

5. The error correction circuit of claim 1 , wherein:
the error correction circuit uses the ECC to correct q error bits of the main data, wherein q is an integer greater than zero; and
the column vectors in the code groups have elements such that a sub codeword group of the plurality of sub codeword groups including a miscorrected bit generated by (q+1) error bits of the main data differs from at least one sub codeword group of the plurality of sub codeword groups including the (q+1) error bits,
wherein the miscorrected bit is a bit that has been erroneously corrected due to error bits in the main data.

6. The error correction circuit of claim 1 , wherein the ECC engine comprises:
an ECC encoder configured to perform an ECC encoding operation on the main data using the ECC to generate the first parity data in a write operation of the semiconductor memory device; and
an ECC decoder configured to perform an ECC decoding operation on the main data based on the first parity data using the ECC in a read operation of the semiconductor memory device.

7. The error correction circuit of claim 6 , wherein the ECC decoder comprises:
a check bit generator configured to generate check bits based on the main data using the ECC;
a syndrome generator configured to generate syndrome data based on a comparison of the check bits and the first parity data; and
a data corrector configured to correct the at least one error bit in the main data.

8. A semiconductor memory device, comprising:
a memory cell array including a plurality of bank arrays,
wherein each of the plurality of bank arrays includes a normal cell region that stores main data, and a redundancy cell region that stores first parity data associated with the main data;
an error correction circuit configured to generate the first parity data based on the main data using an error correction code (ECC), and to correct at least one error bit in the main data using the first parity data, wherein the ECC is represented by a generation matrix and the at least one error bit comprises a first error it and a second error bit; and
a control logic circuit configured to control the error correction circuit based on a command and an address,
wherein the main data includes a plurality of data bits divided into a plurality of sub codeword groups,
wherein the ECC includes a plurality of column vectors divided into a plurality of code groups corresponding to the sub codeword groups,
wherein a first code group corresponding to a first sub codeword group includes a plurality of first column vectors, and a second code group corresponding to a second sub codeword group includes a plurality of second column vectors,
wherein, when the first sub codeword group includes the first error bit and the second sub codeword group includes the second error bit, the first column vectors and the second column vectors are arranged in bit configurations such that a result of a bit-wise exclusive OR operation of each of the first column vectors and each of the second column vectors matches with one of the column vectors in the code groups other than the first code group and the second code group.

9. The semiconductor memory device of claim 8 , wherein:
when the first sub codeword group includes the first error bit and the second error bit, the first column vectors are arranged in bit configurations such that a result of the bit-wise exclusive OR operation of two different column vectors of the first column vectors differs from each of the column vectors in the code groups.

10. The semiconductor memory device of claim 8 , wherein:
the main data includes 2 p -bit of the data bits, wherein p is an integer equal to or greater than seven;
the first parity data includes (p+1)-bit parity bits;
the ECC is a single error correction (SEC) code;
the sub codeword groups include the first sub codeword group, the second sub codeword group, a third sub codeword group, and a fourth sub codeword group, and each of the first through fourth sub codeword groups includes 2 p-2 bits; and
the code groups include the first code group, the second code group, a third code group, and a fourth code group corresponding to the first through fourth sub codeword groups, respectively.

11. The semiconductor memory device of claim 8 , wherein:
the memory cell array includes a plurality of dynamic memory cells coupled to a plurality of word-lines and a plurality of bit-lines; and
the memory cell array is a three-dimensional memory cell array.

12. A memory system, comprising:
a memory module including a plurality of data memories and at least one parity memory; and
a memory controller configured to control the plurality of data memories and the at least one parity memory,
wherein each of the plurality of data memories includes a memory cell array that stores a data set corresponding to a

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cha Sang-Uhn
• Kim Myeong-O

Classifications

• G11C2029/0411

  Online error correction · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C2029/0409

  Online test · CPC title

• G11C29/42 Primary

  using error correcting codes [ECC] or parity check · CPC title

• G11C29/72

  with optimized replacement algorithms · CPC title