Dual-mode error-correction code/write-once memory codec

Patent metadata

Field	Value
Publication number	US-9690517-B2
Application number	US-201514720442-A
Country	US
Kind code	B2
Filing date	May 22, 2015
Priority date	May 22, 2015
Publication date	Jun 27, 2017
Grant date	Jun 27, 2017

Abstract

A system for error correction code (ECC) management of write-once memory (WOM) codes includes, for example, a controller for selecting between one of a WOM (Write-Only Memory) mode and an ECC (error correction code) mode. A codec is arranged to operate in the selected mode. The codec while operating in the ECC mode is arranged to identify a bit position of at least one bit error in response to ECC parity bits of a first received data word. The codec while operating in the WOM mode is arranged to receive a WOM-encoded word from an addressed location in a WOM device, to receive a second received data word to be encoded and written to the addressed location, and to generate WOM-encoded word for writing to the addressed location in the WOM device. The WOM-encoded word for writing to the addressed location is optionally ECC encoded.

First claim

What is claimed is:

1. A circuit, comprising:
a controller operable to select one of a WOM (Write-Only Memory) mode and an ECC (error correction code) mode; and
a codec responsive to the controller, operable in the ECC mode to identify a bit position of at least one bit error in response to ECC parity bits of a first received data word, and operable in the WOM mode to receive a WOM-encoded word from an addressed location in a WOM device, to receive a second received data word, and to generate WOM-encoded word for writing to the addressed location in the WOM device, wherein the generated WOM-encoded word is generated in response to the second received data word and includes information from the second received data word.

2. The circuit of claim 1 , wherein the WOM-encoded word is written to the addressed location in the WOM device by changing a block-initialized state of selected bits of WOM-encoded word previously written to the addressed location of the WOM device.

3. The circuit of claim 1 , wherein the first received data word is the same received data word as the second received data word.

4. The circuit of claim 1 , wherein the codec is operable in the ECC mode to generate a syndrome in accordance with the first received data word.

5. The circuit of claim 4 , wherein the codec is operable in the ECC mode to generate the syndrome in accordance with a check matrix.

6. The circuit of claim 5 , wherein the codec is operable in the ECC mode to address a syndrome table in accordance with the generated syndrome.

7. The circuit of claim 6 , wherein the codec is operable in the WOM mode to address a portion of the syndrome table in accordance with the second received data word.

8. The circuit of claim 7 , the codec comprising a counter operable to generate a first candidate data word for addressing a first portion of the syndrome table.

9. The circuit of claim 8 , the codec comprising a comparator operable to generate a second candidate data word for addressing a second portion of the syndrome table.

10. The circuit of claim 9 , wherein the comparator operable to generate a second candidate data word generates the second candidate data word in response to a comparison of a first delta value and the first candidate data word.

11. The circuit of claim 10 , wherein the first delta value is generated in response to comparing the second received data word to a decoded WOM word, wherein the decoded WOM word is decoded in response to the WOM-encoded word received from the addressed location in the WOM device.

12. The circuit of claim 9 , wherein a second delta word is generated in response to an output of the first portion of the syndrome table and in response to an output of the second portion of the syndrome table.

13. The circuit of claim 12 , wherein the second delta word is written to the addressed location in the WOM device in response to a comparison of the second delta word to the WOM-encoded word received from the addressed location in the WOM device.

14. A system, comprising:
a host processor operable to select one of a WOM (Write-Only Memory) mode and an ECC (error correction code) mode;
a WOM device communicatively coupled to the host processor and operable to be block-initialized in accordance with a block-initialized state; and
a codec responsive to the processor, operable in the ECC mode to identify a bit position of at least one bit error in response to ECC parity bits of a first received data word, and operable in the WOM mode to receive a WOM-encoded word from an addressed location in the WOM device, to receive a second received data word, and to generate WOM-encoded word for writing to the addressed location in the WOM device, wherein the generated WOM-encoded word is generated in response to the second received data word and includes information from the second received data word.

15. The circuit of claim 14 , wherein the codec is operable in the ECC mode to generate a syndrome in accordance with the first received data word and to address a syndrome table in accordance with the generated syndrome.

16. The circuit of claim 15 , wherein the codec is operable in the WOM mode to address a portion of the syndrome table in accordance with the second received data word.

17. The circuit of claim 16 , wherein a second delta word is generated in response to an output of the first individually addressed portion of the syndrome table and in response to an output of the second individually addressed portion of the syndrome table, wherein the first individually addressed portion is addressed separately from the second individually addressed portion, and wherein the second delta word is written to the addressed location in the WOM device in response to a comparison of the second delta word to the WOM-encoded word received from the addressed location in the WOM device.

Assignees

• Texas Instruments Inc

Inventors

• Zhang Sai
• Zhu Yuming
• Bittlestone Clive
• Ramaswamy Srinath

Classifications

• G06F3/0673 Primary

  Single storage device · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• H03M13/159

  Remainder calculation, e.g. for encoding and syndrome calculation · CPC title

• G06F11/1044 Primary

  with specific ECC/EDC distribution · CPC title

• H03M13/353

  Adaptation to the channel · CPC title