Semiconductor memory device, memory system including the same, and method of error correction of the same

Patent metadata

Field	Value
Publication number	US-2016350181-A1
Application number	US-201615156804-A
Country	US
Kind code	A1
Filing date	May 17, 2016
Priority date	Jun 1, 2015
Publication date	Dec 1, 2016
Grant date	—

Abstract

A semiconductor memory device capable of detecting a miscorrected bit generated in the semiconductor memory device outside the semiconductor memory device and a memory system including the semiconductor memory device are disclosed. The semiconductor memory device may generate first check bits based on first data received from the outside, divide an error correcting code (ECC) code word including the first data and the first check bits into a plurality of code word groups, and dispose a miscorrected bit, caused by error bits included in a first ECC code word group, in another ECC code word group rather than the first ECC code word group.

First claim

What is claimed is:

1 . A method of correcting an error in a semiconductor memory device including a memory cell array which includes a plurality of memory cell groups each including a plurality of memory cells, the method comprising:
receiving first data from outside the semiconductor memory device; generating first check bits based on the first data so that a miscorrected bit is disposed in another error correcting code (ECC) code word group rather than a first ECC code word group, the miscorrected bit being caused by error bits included in the first ECC code word group; and storing an ECC code word including a plurality of ECC code word groups in the plurality of memory cell groups, each of the plurality of ECC code word groups having the first data and the first check bits.

2 . The method according to claim 1 , further comprising:
generating second check bits based on second data received from the memory cell array; generating syndrome bits based on the second check bits and third check bits received from the memory cell array; decoding the syndrome bits; and correcting the second data based on the decoded syndrome bits.

3 . The method according to claim 1 , wherein if the ECC code word detects and corrects one error bit, and two error bits exist in the first ECC code word group, the miscorrected bit caused by the error bits is configured to be disposed in another ECC code word group rather than the first ECC code word group.

4 . The method according to claim 1 , wherein if the ECC code word detects and corrects k error bits, and k+1 error bits exist in the first ECC code word group, the miscorrected bit caused by the error bits is configured to be disposed in another ECC code word group rather than the first ECC code word group.

5 . The method according to claim 1 , wherein each of the ECC code word groups has 16 bits or 32 bits.

6 . The method according to claim 1 , wherein if a size of the ECC code word is greater than that of a pre-fetch unit, the miscorrected bit is configured to be disposed in a group, which is not pre-fetched, included in the ECC code word.

7 . The method according to claim 1 , wherein the semiconductor memory device is a stacked memory device in which a plurality of chips for transmitting and receiving data and control signals through a through-silicon-via (TSV) are stacked.

8 . A method of correcting an error in a semiconductor memory device including a memory cell array which includes a plurality of memory cell groups each including a plurality of memory cells, the method comprising:
receiving first data from outside the semiconductor memory device; generating first check bits based on the first data; storing an error correcting code (ECC) code word including a plurality of ECC code word groups, each ECC code word group having a plurality of ECC code word sub groups, each ECC code word sub group having the first data and the first check bits in the plurality of memory cell groups; and disposing a miscorrected bit in a first ECC code word sub group or in another ECC code word group rather than the first ECC code word group when the error bits exist only in the first ECC code word sub group of the first ECC code word group and the miscorrected bit caused by the error bits exist in the first ECC code word sub group.

9 . The method according to claim 8 , wherein if the error bits exist in the first ECC code word sub group and a second ECC code word sub group of the first ECC code word group, the miscorrected bit caused by the error bits is configured to be disposed in another ECC code word group rather than the first ECC code word group.

10 . The method according to claim 8 , wherein if the ECC code word detects and corrects one error bit, and two error bits exist in the first ECC code word group, the miscorrected bit caused by the error bits is configured to be disposed in another ECC code word group rather than the first ECC code word group.

11 . The method according to claim 8 , wherein if the ECC code word detects and corrects k error bits, and k+1 error bits exist in the first ECC code word group, the miscorrected bit caused by the error bits is configured to be disposed in another ECC code word group rather than the first ECC code word group.

12 . The method according to claim 8 , wherein each of the ECC code word groups has 16 bits or 32 bits.

13 . The method according to claim 8 , wherein if a size of the ECC code word is greater than that of a pre-fetch unit, the miscorrected bit is configured to be disposed in a group, which is not pre-fetched, included in the ECC code word.

14 . The method according to claim 8 , wherein the semiconductor memory device is a stacked memory device in which a plurality of chips for transmitting and receiving data and control signals through a through-silicon-via (TSV) are stacked.

15 . A semiconductor memory device comprising:
an encoder configured to,
generate first check bits based on received data received from a host,
form an error correcting code (ECC) code word including the received data and the first check bits,
divide the ECC code word into a plurality of ECC code word groups, and
dispose a miscorrected bit in an ECC code word group, the miscorrected bit being caused by error bits in at least one of the plurality of the ECC code word groups;
a memory cell array including a plurality of memory cell groups having a plurality of memory cells, and configured to store the ECC code word; and a decoder configured to,
decode and correct read data received from the memory cell array based on second check bits received from the memory cell array, and output the corrected read data.

16 . The semiconductor memory device according to claim 15 , wherein the semiconductor memory device is configured such that if the semiconductor memory device is able to detect and correct one error bit of the at least one ECC code word, and two error bits exist in a first ECC code word group of the plurality of ECC code word groups, the semiconductor memory device disposes the miscorrected bit in another ECC code word group of the plurality of ECC code word groups rather than the first ECC code word group.

17 . The semiconductor memory device according to claim 15 , wherein the semiconductor memory device is configured such that if the semiconductor memory device is able to detect and correct k error bits of the at least one ECC code word, and k+1 error bits exist in a first ECC code word group of the plurality of ECC code word groups, the semiconductor memory device disposes the miscorrected bit in another ECC code word group of the plurality of ECC code word groups rather than the first ECC code word group.

18 . The semiconductor memory device according to claim 15 , wherein each of the ECC code word groups of the plurality of ECC code word groups has 16 bits or 32 bits.

19 . The semiconductor memory device according to claim 15 , wherein the semiconductor memory device is configured such that if a size of the ECC code word is greater than that of a pre-fetch unit, the semiconductor memory device disposes the miscorrected bit in a group, which is not pre-fetched, included in the ECC code word.

20 . The semiconductor memory device according to claim 15 , wherein the semiconductor memory device is a stacked memory device in which a plurality of chips for transmitting and receiving data and control signals through a through-silicon-via (TSV) are stacked.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cha Sanguhn
• Chung Hoiju
• Kang Uksong
• Park Chulwoo

Classifications

• G11C29/52 Primary

  Protection of memory contents; Detection of errors in memory contents · CPC title

• H03M13/1575

  Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance · CPC title

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title

• G11C7/10 Primary

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title