Vertical field effect transistor and semiconductor device including the same

Patent metadata

Field	Value
Publication number	US-10629729-B2
Application number	US-201816044584-A
Country	US
Kind code	B2
Filing date	Jul 25, 2018
Priority date	Sep 11, 2017
Publication date	Apr 21, 2020
Grant date	Apr 21, 2020

Abstract

A vFET includes a first impurity region doped with first impurities at an upper portion of the substrate. A first diffusion control pattern is formed on the first impurity region. The first diffusion control pattern is configured to control the diffusion of the first impurities. A channel extends in a vertical direction substantially orthogonal to an upper surface of the substrate. A second impurity region is doped with second impurities on the channel. A second diffusion control pattern is between the channel and the second impurity region. The second diffusion control pattern is configured to control the diffusion of the second impurities. A gate structure is adjacent to the channel.

First claim

What is claimed is:

1. A vertical field effect transistor (vFET), comprising:
a first impurity region including silicon doped with first impurities at an upper portion of a substrate;
a first diffusion control pattern on the first impurity region, the first diffusion control pattern being configured to control the diffusion of the first impurities, the first diffusion control pattern having a lower portion and an upper portion sequentially stacked, the lower portion including silicon-germanium doped with the first impurities, and the upper portion including undoped silicon-germanium or silicon-germanium doped with impurities having a conductivity type different from that of the first impurities;
a channel extending in a vertical direction on the first diffusion control pattern, the vertical direction substantially orthogonal to an upper surface of the substrate;
a second impurity region including silicon doped with second impurities on the channel;
a second diffusion control pattern between the channel and the second impurity region, the second diffusion control pattern being configured to control the diffusion of the second impurities, the second diffusion control pattern having a lower portion and an upper portion sequentially stacked, the upper portion including silicon-germanium doped with the second impurities, and the lower portion including undoped silicon-germanium or silicon-germanium doped with impurities having a conductivity type different from that of the second impurities; and
a gate structure adjacent to the channel, the gate structure covering only a portion of a sidewall of the channel such that a vertical length of a portion of the gate structure covering the portion of the sidewall of the channel is less than a vertical length of the channel.

2. The vFET of claim 1 , further comprising:
a first electrode on the second impurity region; and
a second electrode on the first impurity region, the second electrode being spaced apart from the gate structure.

3. The vFET of claim 2 , wherein a central upper portion of the second impurity region has a sharp upper surface, and
wherein the vFET further comprises a metal silicide pattern between the second impurity region and the first electrode, the metal silicide pattern covering the upper surface of the second impurity region.

4. The vFET of claim 2 , wherein top surfaces of the first and second electrodes are substantially coplanar with each other.

5. The vFET of claim 1 , further comprising a spacer under the gate structure, the spacer covering a lower portion of the channel.

6. The vFET of claim 5 , wherein the spacer includes:
a first pattern covering a lower sidewall of the channel and including silicon oxide; and
a second pattern conformally disposed on the first pattern, the second pattern including silicon nitride.

7. The vFET of claim 1 , wherein the gate structure includes:
a gate insulation pattern disposed on a central sidewall of the channel and including a high-k dielectric material; and
a gate electrode on the gate insulation pattern, the gate electrode including a metal.

8. A semiconductor device, comprising:
a first impurity region doped with first impurities at an upper portion of a substrate;
a first diffusion control pattern on the first impurity region, the first diffusion control pattern being configured to control the diffusion of the first impurities, the first diffusion control pattern having a lower portion and upper portions, the upper portions being spaced apart from each other along a direction parallel to an upper surface of the substrate and protruding from the lower portion in a vertical direction substantially orthogonal to the upper surface of the substrate, the lower portion including silicon-germanium doped with the first impurities, and the upper portions including undoped silicon-germanium or silicon-germanium doped with impurities having a conductivity type different from that of the first impurities;
channels on the respective upper portions of the first diffusion control pattern, each of the channels extending in the vertical direction;
a second impurity region doped with second impurities positioned above the channels;
a second diffusion control pattern between each of the channels and the second impurity region, the second diffusion control pattern being configured to control the diffusion of the second impurities, the second diffusion control pattern having a lower portion and an upper portion sequentially stacked, the upper portion including silicon-germanium doped with the second impurities, and the lower portion including undoped silicon-germanium or silicon-germanium doped with impurities having a conductivity type different from that of the second impurities; and
gate structures adjacent to the channels, respectively, the gate structures partially covering sidewalls of the respective channels such that vertical lengths of portions of the gate structures covering the sidewalls of the respective channels are less than vertical lengths of the respective channels,
wherein distances in the vertical direction from the portions of the gate structures covering the sidewalls of the respective channels to the upper portions of the respective second diffusion control patterns are substantially constant, and
wherein distances in the vertical direction from the portions of the gate structures covering the sidewalls of the respective channels to the lower portion of the first diffusion control pattern are substantially constant.

9. The semiconductor device of claim 8 , wherein the gate structures are connected with each other to form a single gate structure.

10. The semiconductor device of claim 8 , further comprising a spacer positioned on lower portions of the channels and the upper portions of the first diffusion control pattern.

11. The semiconductor device of claim 8 , wherein the second impurity region has an uneven upper surface, and
wherein the semiconductor device further comprises:
a metal silicide pattern covering the upper surface of the second impurity region;
a first electrode on the metal silicide pattern; and
a second electrode on the first impurity region, the second electrode being spaced apart from the gate structures.

12. A semiconductor device, comprising:
first diffusion control patterns spaced apart from each other on a substrate;
first impurity regions doped with first impurities at upper portions of the substrate below the first diffusion control patterns, respectively;
channels on the first diffusion control patterns, respectively, each of the channels extending in a vertical direction substantially orthogonal to an upper surface of the substrate;
a second impurity region doped with second impurities positioned above the channels;
a second diffusion control pattern between each of the channels and the second impurity region, the second diffusion control pattern being configured to control the diffusion of the second impurities; and
gate structures adjacent to the channels, respectively, the gate structures partially covering sidewalls of the respective channels such that vertical lengths of portions of the gate structures covering the sidewalls of the respective channels are less than vertical lengths of the respective channels,
wherein each of the first diffusion control patterns has a lower portion and an upper portion sequentially stacked, the lower portion including silicon-germanium doped with the first impurities, and the upper portions including undoped silicon-germanium or silicon-germanium doped with impurities having a conductivity type different from that of the first impurities,
wherein each of the second dif

Assignees

• Samsung Electronics Co Ltd

Inventors

• You Jung-Gun
• Kim Chang-Hee
• Park Sung-Il
• Lee Dong-Hun

Classifications

• H01L29/66553

  Electricity · mapped topic

• H01L21/823885

  Electricity · mapped topic

• H01L21/823481

  Electricity · mapped topic

• H01L21/3083

  Electricity · mapped topic

• H01L21/823842

  Electricity · mapped topic