Reducing direct source-to-drain tunneling in field effect transistors with low effective mass channels

Patent metadata

Field	Value
Publication number	US-9564514-B2
Application number	US-201514931930-A
Country	US
Kind code	B2
Filing date	Nov 4, 2015
Priority date	Nov 21, 2014
Publication date	Feb 7, 2017
Grant date	Feb 7, 2017

Abstract

An approach to providing a barrier in a vertical field effect transistor with low effective mass channel materials wherein the forming of the barrier includes forming a first source/drain contact on a semiconductor substrate and forming a channel with a first channel layer on the first source/drain contact. The approach further includes forming the barrier on the first channel layer, and a second channel layer on the barrier followed by forming a second source/drain contact on the second channel layer.

First claim

What is claimed is:

1. A semiconductor structure with a barrier for field effect transistors with low effective mass channel materials, comprising:
a semiconductor substrate;
a first source/drain layer on the semiconductor substrate;
a first channel layer on the first source/drain layer;
a barrier layer on the first channel layer;
a second channel layer on the barrier layer, wherein the barrier layer is composed of a first semiconductor material with a lower electron affinity than a semiconductor material of the first channel layer and the second channel layer in a n-type field effect transistor;
a second source/drain layer on the second channel layer;
a gate electrode around a gate dielectric layer and over the gate dielectric layer on a portion of the first source/drain layer, the gate dielectric layer around at least a first dielectric spacer;
a second dielectric spacer surrounding the gate electrode;
a contact metal layer contacting the first source/drain layer and surrounding the second dielectric spacer; and
an interlayer dielectric over the gate dielectric layer on the portion of the first source/drain layer and surrounding the contact metal layer.

2. The semiconductor structure of claim 1 , wherein the first channel layer and the second channel layer are composed of a same semiconductor material and have a same doping.

3. The semiconductor structure of claim 1 , wherein the barrier layer is composed of a group III-V semiconductor material in an n-type field effect transistor.

4. The semiconductor structure of claim 1 , wherein the barrier layer is composed of a group IV semiconductor material or a compound group IV semiconductor material in a p-type field effect transistor.

5. The semiconductor structure of claim 1 , wherein the barrier layer is doped in a range 10 16 cm −3 to 10 18 cm −3 with a channel type doping material.

6. The semiconductor structure of claim 1 , further comprises wherein the barrier layer is in a center of the first channel layer and the second channel layer.

7. The semiconductor structure of claim 1 , wherein the barrier layer has a bandgap in a range of 1 eV to 2 eV.

8. The semiconductor structure of claim 1 , wherein a thickness of the barrier layer is in a range 2 nm to 10 nm.

9. The semiconductor structure of claim 1 , further comprising a gate dielectric layer deposited over the semiconductor structure, wherein the gate dielectric layer is a high-k dielectric material.

10. The semiconductor structure of claim 1 , wherein the first source/drain layer, the first channel layer, the second channel layer, and the barrier are circular in shape and form a pillar.

11. The semiconductor structure of claim 1 , further comprises:
wherein the first dielectric spacer surrounds the second channel layer, the second source/drain layer and a contact metal layer on the second source/drain layer;
wherein the gate dielectric layer is around the second source/drain layer, the first channel layer, the barrier layer, the second channel layer, and at least the first dielectric spacer, and on the portion of the first source/drain layer; and
wherein the second dielectric spacer surrounds a gate metal contact over a portion of the gate electrode.

Assignees

• IBM

Inventors

• Basu Anirban
• Majumdar Amlan
• Sleight Jeffrey W

Classifications

• H01L29/78681

  Electricity · mapped topic

• H01L29/7827

  Electricity · mapped topic

• H01L29/41741

  Electricity · mapped topic

• H01L29/78642

  Electricity · mapped topic

• H01L29/6656

  Electricity · mapped topic