Semiconductor device having buried bit lines and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-9443858-B2
Application number	US-201414547960-A
Country	US
Kind code	B2
Filing date	Nov 19, 2014
Priority date	Aug 28, 2012
Publication date	Sep 13, 2016
Grant date	Sep 13, 2016

Abstract

A semiconductor device includes semiconductor bodies formed substantially perpendicular to a semiconductor substrate, buried bit lines formed in the semiconductor bodies and including a metal silicide; and barrier layers formed under and over the buried bit lines and containing germanium.

First claim

What is claimed is:

1. A method for fabricating a semiconductor device, comprising:
forming semiconductor bodies in which a first barrier layer, a silicon layer and a second barrier layer are stacked over a semiconductor substrate and that includes channel regions of vertical channel transistors;
forming source/drain regions under the first barrier layer and over the second barrier layer; and
forming buried bit lines by silicidating the silicon layer after the forming of source/drain regions,
wherein the first barrier layer and the second barrier layer include silicon germanium.

2. The method according to claim 1 , wherein a content of germanium in the first barrier layer and a content of germanium in the second barrier layer, respectively, is at least approximately 30%.

3. The method according to claim 1 , wherein the forming of the semiconductor bodies comprises:
forming a stack layer in which the first barrier layer, the silicon layer and the second barrier layer are sequentially stacked, over the semiconductor substrate; and
selectively etching the stack layer, thereby defining trenches and forming the semiconductor bodies with both sidewalls, which are separated from one another by the trenches.

4. The method according to claim 1 , wherein the first barrier layer, the silicon layer and the second barrier layer are formed through epitaxial growth.

5. The method according to claim 1 , wherein the forming of the buried bit lines comprises:
forming a passivation layer that covers sidewalls of the semiconductor bodies, exposing sidewalls of the silicon layer;
forming a metal-containing layer over entire surfaces of the semiconductor bodies including the passivation layer;
forming a metal silicide layer by reacting the silicon layer and the metal-containing layer with each other through annealing; and
removing the portion of the metal-containing layer, which is not reacted.

6. The method according to claim 1 , wherein the buried bit lines comprise a cobalt silicide.

7. A method for fabricating a semiconductor device, comprising:
forming a stack layer in which a first germanium-containing layer, a first silicon layer, a second germanium-containing layer and a second silicon layer are sequentially stacked, over a silicon substrate;
forming semiconductor bodies that are separated from one another by trenches formed by selectively etching the stack layer;
forming a passivation layer that covers sidewalls of the semiconductor bodies, to expose sidewalls of the first silicon layer;
forming buried bit lines by silicidating the first silicon layer; and
forming a plurality of semiconductor pillars that includes channel regions of vertical channel transistors by etching the second silicon layer
wherein the forming of the buried bit lines comprises:
forming a metal-containing layer on surfaces of the semiconductor bodies including the passivation layer;
forming a metal silicide layer by reacting the metal-containing layer with the first silicon layer through annealing; and
removing the portion of metal-containing layer, which has not reacted.

8. The method according to claim 7 , further comprising:
forming storages that are connected with the plurality of semiconductor pillars.

9. The method according to claim 7 , wherein the first germanium-containing layer and the second germanium-containing layer include of silicon germanium.

10. The method according to claim 7 , wherein a content of germanium in the first germanium-containing layer and a content of germanium in the second germanium-containing layer, respectively, is at least approximately 30%.

11. The method according to claim 7 , wherein the first germanium-containing layer, the first silicon layer, the second germanium-containing layer and the second silicon layer are formed through epitaxial growth.

12. The method according to claim 7 , wherein the forming of the passivation layer comprises:
forming a first passivation layer along surfaces of structures including the semiconductor bodies;
forming a sacrificial layer to fill lower portions of the trenches;
forming a second passivation layer on both sidewalls of the semiconductor bodies including the first passivation layer;
recessing the sacrificial layer by a predetermined thickness, thereby exposing a portion of the first passivation layer formed on sidewalls of the first silicon layer; and
removing the exposed portion of the first passivation layer.

13. The method according to claim 12 , wherein the sacrificial layer that fills the lower portions of the trenches is formed so that an upper surface of the sacrificial layer is positioned between an upper surface and a lower surface of the second germanium-containing layer.

14. The method according to claim 12 , wherein the sacrificial layer that is recessed is formed so that an upper surface of the sacrificial layer is positioned between an upper surface and a lower surface of the first germanium-containing layer.

15. The method according to claim 7 , wherein the buried bit lines comprise a cobalt silicide.

16. The method according to claim 1 , wherein the forming of the buried bit lines is performed by fully silicidating the silicon layer.

Assignees

• Sk Hynix Inc

Inventors

• Myung Ju-Hyun
• Hwang Eui-Seong
• Park Eun-Shil
• Kim Tae-Yoon

Classifications

• H10D64/2523

  for vertical devices wherein the source or drain electrodes extend entirely through semiconductor bodies · CPC title

• H10D30/63 Primary

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H10P32/1204

  from a plasma phase · CPC title

• H10W20/021

  of interconnections within wafers or substrates · CPC title

• H10D30/025

  of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318) · CPC title