Passive devices for integration with three-dimensional memory devices

Patent metadata

Field	Value
Publication number	US-9589981-B2
Application number	US-201514739354-A
Country	US
Kind code	B2
Filing date	Jun 15, 2015
Priority date	Jun 15, 2015
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

A three dimensional memory device includes a memory device region containing a plurality of non-volatile memory devices, a peripheral device region containing active driver circuit devices, and a stepped surface region between the peripheral device region and the memory device region containing a plurality of passive driver circuit devices.

First claim

What is claimed is:

1. A semiconductor device, comprising:
an alternating stack of first material layers and second material layers located over a substrate;
at least one pillar structure extending from a first horizontal plane including a top surface of the alternating stack through at least a portion of the alternating stack;
a laterally-extending semiconductor or conductive structure contacting a bottom surface of the at least one pillar structure;
a contact via structure contacting a top surface of the laterally-extending semiconductor or conductive structure and laterally spaced from the at least one pillar structure;
a memory opening extending through the alternating stack; and
a memory stack structure that comprises a memory film located within the memory opening, and a semiconductor channel located within the memory film;
wherein:
each of the at least one pillar structure comprises at least one doped semiconductor material portion therein;
each semiconductor material portion within the at least one pillar structure has a doping of a same second conductivity type;
the at least one pillar structure comprises at least a portion of a resistor;
each of the at least one pillar structure comprises a layer stack of at least two dielectric material layers located on an outer sidewall of a respective set of at least one doped semiconductor material portion;
the memory film and the layer stack of at least two dielectric material layers comprise an identical set of dielectric materials;
the laterally-extending semiconductor or conductive structure consists of at least one single crystalline semiconductor material portion located in the substrate;
the at least one doped semiconductor material portion comprises a same semiconductor material as the semiconductor channel, and further includes electrical dopants of the same second conductivity type; and
the semiconductor channel is intrinsic or has a doping of a first conductivity type that is the opposite of the second conductivity type.

2. The semiconductor structure of claim 1 , wherein:
the memory stack structure further comprises a drain region having a same second conductivity type of doping as the least one doped semiconductor material portion; and
a second doped semiconductor material portion of the at least one doped semiconductor material portion comprises a same semiconductor material as the drain region.

3. A semiconductor device, comprising:
an alternating stack of first material layers and second material layers located over a substrate;
at least one pillar structure extending from a first horizontal plane including a top surface of the alternating stack through at least a portion of the alternating stack;
a laterally-extending semiconductor or conductive structure contacting a bottom surface of the at least one pillar structure;
a contact via structure contacting a top surface of the laterally-extending semiconductor or conductive structure and laterally spaced from the at least one pillar structure; and
additional resistor structures, each additional resistor structure comprising:
at least one additional pillar structure extending from the first horizontal plane to a respective electrically conductive layer located at a different level from the laterally-extending semiconductor or conductive structure;
a respective electrically conductive layer contacting a bottom surface of the at least one additional pillar structure; and
an additional contact via structure contacting a top surface of the respective electrically conductive layer;

wherein:
each of the at least one pillar structure comprises at least one doped semiconductor material portion therein;
each semiconductor material portion within the at least one pillar structure has a doping of a same second conductivity type;
the first material layers comprise electrically insulating layers;
the second material layers comprise electrically conductive layers;
the laterally-extending semiconductor or conductive structure comprises one of the electrically conductive layers;
each of the at least one pillar structure consists of a respective doped semiconductor material portion;
the alternating stack comprises a stepped surface region in which each electrically conductive layer having at least one overlying electrically conductive layer laterally extends farther than any overlying electrically conductive layer;
a retro-stepped dielectric material portion overlies the stepped surface region; and
the at least one pillar structure, the laterally-extending semiconductor or conductive structure, and the contact via structure collectively constitute a resistor structure.

4. A semiconductor device, comprising:
an alternating stack of first material layers and second material layers located over a substrate;
at least one pillar structure extending from a first horizontal plane including a top surface of the alternating stack through at least a portion of the alternating stack;
a laterally-extending semiconductor or conductive structure contacting a bottom surface of the at least one pillar structure;
a contact via structure contacting a top surface of the laterally-extending semiconductor or conductive structure and laterally spaced from the at least one pillar structure; and
a vertical NAND memory device located over the substrate, wherein:
the vertical NAND memory device comprises a memory stack structure extending through an alternating stack of electrically insulating layers located at each level of the first material layers and electrically conductive layers located at each level of the second material layers;
the electrically conductive layers comprise, or are electrically connected to, a respective word line of the vertical NAND memory device;
the substrate comprises a silicon substrate;
the vertical NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in the first device level of the three-dimensional array of NAND strings is located over another memory cell in the second device level of the three-dimensional array of NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and
the three-dimensional array of NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the silicon substrate;
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the silicon substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level;

wherein:
each of the at least one pillar structure comprises at least one doped semiconductor material portion therein;
each semiconductor material portion within the at least one pillar structure has a doping of a same second conductivity type; and
the at least one pillar structure comprises at least a portion of a resistor located in at least one of a kerf region, a first stepped surface region between a peripheral device region and a memory device region, a second stepped surface region which comprises a stepped track between the kerf region and the peripheral device region, and a third stepped surface region which comprises a word line contact region containing word line contact via structures.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Nishikawa Masatoshi
• Honma Ryoichi
• Miwa Toru
• Koketsu Hiroaki
• Alsmeier Johann

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10P14/416

  of highly doped semiconductor materials, e.g. polysilicon layers or amorphous silicon layers · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title