Semiconductor package having a high reliability

US10622335B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10622335-B2
Application numberUS-201816200109-A
CountryUS
Kind codeB2
Filing dateNov 26, 2018
Priority dateFeb 22, 2016
Publication dateApr 14, 2020
Grant dateApr 14, 2020

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurality of underfill fillets. The plurality of underfill fillets include a plurality of protrusions that protrude from spaces between each of tire plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. At least two neighboring underfill fillet protrusions of the plurality of protrusions form one continuous structure without an interface therebetween.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of fabricating a semiconductor package, the method comprising: providing a package substrate and a plurality of semiconductor devices, each of the plurality of semiconductor devices having connection terminals and a pre-applied underfill film on a surface; stacking the plurality of semiconductor devices on the package substrate at a first temperature; heating the plurality of semiconductor devices to a second temperature higher than the first temperature so that the pre-applied underfill film is reflowed to form a plurality of underfill fillets, each underfill fillet having a convex surface; and molding the plurality of semiconductor devices, wherein in heating the plurality of semiconductor devices to the second temperature, at least two neighboring underfill fillets form one continuous structure without an interface therebetween. 2. The method of claim 1 , wherein the heating of the plurality of semiconductor devices to a second temperature is performed after the stacking of the plurality of semiconductor devices. 3. The method of claim 1 , wherein the pre-applied underfill film includes at least one of a non-conductive film (NCF), a non-conductive paste (NCP), and an anisotropic conductive film (ACF). 4. The method of claim 1 , wherein the plurality of semiconductor devices are coupled with each other depending on viscosity of the pre-applied underfill film during the stacking of the plurality of semiconductor devices. 5. The method of claim 1 , wherein pressure is applied to the plurality of semiconductor devices while heating the plurality of semiconductor devices to a second temperature. 6. The method of claim 1 , wherein the pre-applied underfill films are reflowed and form a plurality of protrusions that protrude front spaces between each of the plurality of semiconductor devices or between the package substrate and each of the plurality of semiconductor devices. 7. The method of claim 6 , wherein the at least two neighboring underfill filets form one continuous structure by a flowing together of corresponding protrusions thereof. 8. The method of claim 1 , further comprising curing the plurality of underfill fillets by cooling the plurality of semiconductor devices, after heating the plurality of semiconductor devices to a second temperature higher than the first temperature. 9. The method of claim 8 , wherein the cooling of the plurality of semiconductor devices is not performed before heating the plurality of semiconductor devices to the second temperature higher than the first temperature. 10. The method of claim 8 , wherein intervals between the plurality of semiconductor devices, and between the package substrate and the plurality of semiconductor devices get smaller for semiconductor devices further away from the package substrate after the curing. 11. The method of claim 1 , wherein the first temperature ranges from about 80° C. to about 100° C. 12. The method of claim 1 , wherein the second temperature ranges from about 220° C. to about 280° C. 13. A method of fabricating a semiconductor package, the method comprising: providing a package substrate, a first semiconductor device, and a second semiconductor device, the first semiconductor device having a first pre-applied underfill film and the second semiconductor device having a second pre-applied underfill film; stacking the first semiconductor device and the second semiconductor device sequentially on the package substrate; simultaneously reflowing the first pre-applied underfill film and the second pre-applied underfill film so that the first pre-applied underfill film and the second pre-applied underfill film flow and form one continuous structure without an interface therebetween. 14. The method of claim 13 , wherein at least one of the first semiconductor device and the second semiconductor device is a sub-package and the semiconductor package is a package-on-package (PoP) type of package. 15. The method of claim 13 , further comprising curing the one continuous structure by cooling after the reflowing. 16. The method of claim 15 , wherein the one continuous structure has a side surface having convex portions at the levels of the first pre-applied underfill film and the second pre-applied underfill film. 17. The method of claim 15 , further comprising molding the first semiconductor device and the second semiconductor device with molding resin. 18. The method of claim 17 , wherein the upper surface of the second semiconductor device is coplanar with an upper surface of the molding resin at a first plane. 19. The method of claim 18 , wherein the one continuous structure is partially exposed at the first plane. 20. A method of fabricating a semiconductor package, the method comprising: providing a package substrate and a plurality of semiconductor devices, each of the plurality of semiconductor devices having connection terminals and a pre-applied underfill film on a surface; stacking the plurality of semiconductor devices on the package substrate at a first temperature; heating the plurality of semiconductor devices to a second temperature higher than the first temperature so that the pre-applied underfill film is reflowed to form a plurality of underfill fillets, each underfill fillet having a convex surface; and curing the plurality of underfill fillets by cooling, wherein, after the curing, intervals between the plurality of semiconductor devices, and between the package substrate and the plurality of semiconductor devices get smaller for semiconductor devices further away from the package substrate.

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What does patent US10622335B2 cover?
A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the package substrate and the plurality of semiconductor devices, and a molding resin at least partially surrounding the plurality of semiconductor devices and the plurali…
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification H01L25/0657. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Apr 14 2020 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).