LDMOS transistor and method

Patent metadata

Field	Value
Publication number	US-10622284-B2
Application number	US-201615192283-A
Country	US
Kind code	B2
Filing date	Jun 24, 2016
Priority date	Jun 24, 2016
Publication date	Apr 14, 2020
Grant date	Apr 14, 2020

Abstract

In an embodiment, a semiconductor device includes a semiconductor substrate, a LDMOS transistor arranged in a front surface of the semiconductor substrate and a conductive through substrate via. The conductive through substrate via includes a via extending from the front surface to a rear surface of the semiconductor substrate, a conductive plug filling a first portion of the via and a conductive liner layer lining side walls of a second portion of the via and electrically coupled to the conductive plug.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a semiconductor substrate;
a LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistor arranged in a front surface of the semiconductor substrate; and
a conductive through substrate via,
wherein the conductive through substrate via comprises:
a via extending from the front surface to a rear surface of the semiconductor substrate;
a conductive plug filling a first portion of the via, and
a conductive liner layer lining side walls of a second portion of the via and electrically coupled to the conductive plug,
wherein the through substrate via is formed between semiconductor sidewalls that vertically extend between the front and rear surfaces of the semiconductor substrate,
wherein the conductive plug comprises an upper surface laterally extending between the semiconductor sidewalls and a rear surface which is coplanar with the rear surface of the semiconductor substrate and opposite from the upper surface,
wherein vertical portions of the conductive liner layer vertically extend from the front surface to the upper surface of the conductive plug along the semiconductor sidewalls, and
wherein a lateral portion of the conductive liner laterally extends between the semiconductor sidewalls along the upper surface of the conductive plug.

2. The semiconductor device of claim 1 , wherein the conductive liner layer is positioned directly on the conductive plug, forming an interface therebetween.

3. The semiconductor device of claim 1 , wherein the conductive plug comprises a grain size that is larger than a grain size of the conductive liner layer.

4. The semiconductor device of claim 1 , wherein the conductive liner layer surrounds a gap within the via.

5. The semiconductor device of claim 1 , wherein the conductive through substrate via electrically couples an intrinsic source of the LDMOS transistor arranged in the front surface of the semiconductor substrate to a conductive layer arranged on a rear side of the semiconductor substrate.

6. The semiconductor device of claim 1 , wherein the semiconductor substrate has a bulk resistivity ρ>100 Ohm.cm.

7. The semiconductor device of claim 1 , wherein the conductive through substrate via has a height h 1 and the conductive plug has a height h 2 , wherein h 2 ≤2h 1 /3.

8. The semiconductor device of claim 7 , wherein 20 μm≤h 1 ≤ 100 μm and wherein 5 μm≤h 2 ≤70 μm.

9. The semiconductor device of claim 1 , wherein the conductive liner layer has a thickness t, wherein 0.5 μm≤t≤3 μm, and the conductive plug has a height h 2 , wherein 5 μm≤h 2 ≤70 μm.

10. The semiconductor device of claim 1 , further comprising dielectric material covering the via and defining a cavity within the second portion of the via.

11. The semiconductor device of claim 10 , wherein the dielectric material comprises a first layer arranged on the conductive liner layer and a second layer capping the via to define the cavity.

12. The semiconductor device of claim 11 , wherein the first layer comprises SiN x and the second layer comprises SiO x .

13. The semiconductor device of claim 1 , wherein a plurality of conductive through substrate vias are arranged in a regular array.

14. The semiconductor device of claim 1 , wherein a plurality of conductive through substrate vias are arranged in at least one row adjacent an elongate intrinsic source of the LDMOS transistor.

15. The semiconductor device of claim 1 , wherein the conductive through substrate via is electrically coupled to an intrinsic source of two neighbouring transistor cells of the LDMOS transistor.

16. The semiconductor device of claim 1 , wherein the conductive liner layer extends onto the first surface of the semiconductor substrate adjacent the via.

17. The semiconductor device of claim 16 , further comprising a lateral conductive layer extending on the front surface of the semiconductor substrate between the conductive liner layer and an intrinsic source of the LDMOS transistor, wherein the conductive liner layer is arranged on a portion of the lateral conductive layer.

18. The semiconductor device of claim 17 , wherein the lateral conductive layer and the conductive liner layer comprise different conductive materials.

19. The semiconductor device of claim 17 , wherein the lateral conductive layer comprises Ti and the conductive liner layer comprises Cu.

20. The semiconductor device of claim 18 , wherein the conductive liner layer has a thickness t and the lateral conductive layer has a thickness t 1 , wherein t/25≤t 1 ≤t/2.

21. The semiconductor device of claim 1 , wherein the conductive through substrate via further comprises a barrier layer structure in direct contact with the front surface of the semiconductor substrate in regions adjacent the via and further extending on and making direct contact with the semiconductor sidewalls, wherein the conductive plug and the conductive liner layer are arranged on the barrier layer structure.

Assignees

• Infineon Technologies Ag

Inventors

• Birner Albert
• Brech Helmut
• Zigldrum Matthias

Classifications

• H01L21/76898

  Electricity · mapped topic

• H01L21/76834

  Electricity · mapped topic

• H01L23/53228

  Electricity · mapped topic

• H01L29/063

  Electricity · mapped topic

• H01L21/2885

  Electricity · mapped topic