Method of forming a semiconductor device and structure therefor

Patent metadata

Field	Value
Publication number	US-9245952-B2
Application number	US-201414275176-A
Country	US
Kind code	B2
Filing date	May 12, 2014
Priority date	May 12, 2014
Publication date	Jan 26, 2016
Grant date	Jan 26, 2016

Abstract

In one embodiment, a method of forming a semiconductor device may include forming a buried region within a semiconductor region, including forming an opening in the buried region. The method may also include forming a drift region of a second conductivity type in the semiconductor region with at least a portion of the drift region overlying a first portion of the buried region. Another portion of the method may include forming a first drain region of the second conductivity type in the drift region wherein the first drain region does not overlie the buried region.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a semiconductor substrate;
a first semiconductor region formed as a doped region overlying the semiconductor substrate;
a drift region formed as a first doped region of a first conductivity type within the first semiconductor region and overlying the semiconductor substrate, the drift region having a first doping concentration;
a first drain region formed as a second doped region of the first conductivity type within the drift region, the first drain region having a second doping concentration that is greater than the first doping concentration;
a second drain region of the first conductivity type within the first drain region, the second drain region having a third doping concentration that is greater than the second doping concentration;
a body region of a second conductivity type in the first semiconductor region and spaced laterally apart from the drift region;
a source region of the first conductivity type in the body region; and
a buried region of the second conductivity type underlying the source region, at least a portion of the body region, and at least a portion of the drift region but not underlying the first drain region and the second drain region.

2. The semiconductor device of claim 1 wherein the third doping concentration is no less than approximately 1E18 atoms/cm 3 and the second doping concentration is approximately 1E17 to 1E19 atoms/cm 3 .

3. The semiconductor device of claim 1 further including a field insulator extending from a surface of the first semiconductor region a first distance into the semiconductor device wherein the first drain region extends no greater than the first distance into the semiconductor device.

4. The semiconductor device of claim 3 further including a field plate conductor on the field insulator and positioned to overlie a portion of the drift region that is adjacent to the first drain region.

5. The semiconductor device of claim 1 wherein the buried region has a doping concentration that is substantially no less than the first doping concentration and is substantially similar to a doping concentration of the drift region.

6. The semiconductor device of claim 1 wherein the semiconductor device is devoid of another doped region that underlies the buried region and that physically and electrically contacts the buried region.

7. The semiconductor device of claim 1 wherein the semiconductor substrate includes a bulk semiconductor substrate of the first conductivity type, a first layer of the second conductivity type on the bulk semiconductor substrate, a second layer of the second conductivity type on the first layer, and the first semiconductor region on second layer.

8. The semiconductor device of claim 7 further including an isolation region surrounding the body region and the drift region and extending through the first semiconductor region to at least touch the bulk semiconductor substrate.

9. The semiconductor device of claim 7 further including a contact region extending through the first semiconductor region to electrically connect to the second layer.

10. The semiconductor device of claim 1 further including an opening in the buried region with the opening underlying the first drain region and the second drain region with a first portion of the buried region extending away from the opening to underlie the source region and a second portion of the buried region extending away from the opening and underlying a portion of the drift region.

11. The semiconductor device of claim 1 wherein a first portion of the buried region extends to underlie one edge of the drift region and another portion of the buried region extends to underlie another edge of the drift region with an opening formed between the first portion of the buried region and the second portion of the buried region, and wherein the opening underlies the first drain region.

12. The semiconductor device of claim 1 wherein a portion of the first semiconductor region is positioned between the body region and the drift region.

13. The semiconductor device of claim 1 further including another source region of the first conductivity type spaced apart from the source region wherein the first drain region is between the source region and the another source region, the another source region overlying a portion of the buried region.

14. The semiconductor device of claim 8 further including a field insulator on a surface of the semiconductor region and extending a first distance into the semiconductor region wherein the first drain region is within an opening in the field insulator.

Assignees

• Semiconductor Components Ind

Inventors

• Yao Thierry Coffi Herve
• Agam Moshe

Classifications

• H10D62/126

  Top-view geometrical layouts of the regions or the junctions · CPC title

• H10D30/603 Primary

  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS] · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W10/061

  using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title