Automated hybrid metrology for semiconductor device fabrication

Patent metadata

Field	Value
Publication number	US-9330985-B2
Application number	US-201213419286-A
Country	US
Kind code	B2
Filing date	Mar 13, 2012
Priority date	Mar 13, 2012
Publication date	May 3, 2016
Grant date	May 3, 2016

Abstract

Methods and systems are provided for fabricating and measuring features of a semiconductor device structure. An exemplary method of fabricating a semiconductor device structure involves fabricating a feature of the semiconductor device structure on a wafer of semiconductor material, determining a hybrid recipe for measuring the feature, configuring a plurality of metrology tools to implement the hybrid recipe, and obtaining a hybrid measurement of the feature in accordance with the hybrid recipe.

First claim

What is claimed is:

1. A fabrication system comprising:
a processing tool to fabricate a feature of a semiconductor device structure on a wafer of semiconductor material;
a hybrid measurement system including a plurality of metrology tools cooperatively configured to determine a hybrid measurement of the feature, wherein the plurality of metrology tools comprises a primary metrology tool and one or more secondary metrology tools and wherein the primary metrology tool receives or otherwise obtains measurements of the feature from one or more of the secondary metrology tools for use in determining the hybrid measurement of the feature; and
a computing device communicatively coupled to the plurality of metrology tools, wherein the computing device is configured to modify a respective measurement recipe for a respective metrology tool of the plurality of metrology tools to determine the hybrid measurement.

2. The fabrication system of claim 1 , wherein the computing device is configured to:
determine a hybrid recipe for the hybrid measurement based on performance characteristics of the plurality of metrology tools; and
modify the respective measurement recipes for the respective metrology tools of the plurality of metrology tools to implement the hybrid recipe.

3. The fabrication system of claim 2 , wherein the computing device is configured to:
identify physical characteristics of the feature fabricated by the processing tool; and
determine the hybrid recipe for the hybrid measurement of the feature based on the physical characteristics of the feature and the performance characteristics of the plurality of metrology tools.

4. The fabrication system of claim 2 , further comprising an automation system coupled to the computing device, the hybrid recipe including a measurement sequence for the plurality of metrology tools, wherein the computing device is configured to instruct the automation system to transfer the wafer among the plurality of metrology tools in accordance with the measurement sequence.

5. The fabrication system of claim 1 , further comprising a second processing tool to obtain the hybrid measurement from the hybrid measurement system, wherein the second processing tool is configured to fabricate a second feature of the semiconductor device structure on the wafer in a manner that is influenced by the hybrid measurement.

6. The fabrication system of claim 1 , wherein the computing device is configured to:
modify a first measurement recipe of a first metrology tool of the plurality of metrology tools to obtain a first measurement of the feature; and
modify a second measurement recipe of a second metrology tool of the plurality of metrology tools to obtain a second measurement of the semiconductor device structure, wherein the hybrid measurement is determined based at least in part on the first measurement and the second measurement.

7. The fabrication system of claim 6 , further comprising an automation system coupled to the computing device, wherein the computing device is configured to:
determine a measurement sequence for the first metrology tool and the second metrology tool based on performance characteristics of the first metrology tool, performance characteristics of the second metrology tool, and physical characteristics of the feature; and
instruct the automation system to transfer the wafer from the processing tool to the first metrology tool or the second metrology tool in accordance with the measurement sequence.

8. The fabrication system of claim 7 , wherein:
the automation system is configured to:
transfer the wafer from the processing tool to the second metrology tool; and
transfer the wafer from the second metrology tool to the first metrology tool after the second measurement is obtained; and

the first metrology tool is communicatively coupled to the second metrology tool and configured to:
obtain the second measurement; and
determine the hybrid measurement based at least in part on the first measurement and the second measurement.

9. The fabrication system of claim 1 , further comprising an automation system, wherein the computing device is additionally communicatively coupled to the automation system, wherein the computing device is configured to:
determine a hybrid recipe for the hybrid measurement;
configure the plurality of metrology tools to implement the hybrid recipe; and
configure the automation system to transfer the wafer from the processing tool to the plurality of metrology tools in accordance with the hybrid recipe.

10. A method of fabricating a semiconductor device structure, the method comprising:
fabricating a feature of the semiconductor device structure on a wafer of semiconductor material;
determining a hybrid recipe for measuring the feature;
configuring a plurality of metrology tools to implement the hybrid recipe, wherein the plurality of metrology tools comprises a primary metrology tool and one or more secondary metrology tools; and
obtaining a hybrid measurement of the feature in accordance with the hybrid recipe, wherein the primary metrology tool receives or otherwise obtains measurements of the feature from one or more of the secondary metrology tools for use in obtaining the hybrid measurement of the feature.

11. The method of claim 10 , wherein configuring the plurality of metrology tools comprises:
modifying a first measurement recipe of a first metrology tool of the plurality of metrology tools to obtain a first measurement of the semiconductor device structure; and
modifying a second measurement recipe of a second metrology tool of the plurality of metrology tools to obtain a second measurement of the feature, wherein the hybrid measurement is determined based at least in part on the first measurement obtained by the first metrology tool and the second measurement obtained by the second metrology tool.

12. The method of claim 11 , wherein configuring the plurality of metrology tools further comprises:
modifying the second measurement recipe of the second metrology tool to obtain the first measurement; and
modifying an algorithm implemented by the second metrology tool to determine the hybrid measurement based at least in part on the first measurement and the second measurement.

13. The method of claim 11 , wherein obtaining the hybrid measurement comprises:
transferring the wafer to the first metrology tool;
executing, by the first metrology tool, the first measurement recipe to obtain the first measurement;
transferring the wafer to the second metrology tool after the first metrology tool executes the first measurement recipe;
executing, by the second metrology tool, the second measurement recipe to obtain the second measurement; and
determining the hybrid measurement based at least in part on the first measurement and the second measurement.

14. The method of claim 10 , further comprising identifying physical characteristics of the feature, wherein determining the hybrid recipe comprises determining the hybrid recipe based on the physical characteristics of the feature and performance characteristics of the plurality of metrology tools.

15. The method of claim 10 , the hybrid recipe including a sampling plan indicating an order for measuring the wafer using the plurality of metrology tools, wherein obtaining the hybrid measurement comprises configuring an automation system to transfer the wafer among the plurality of metrology tools in the order indicated by the sampling plan.

16. The method of claim 10 , further comprising fabricating a second feature of the semiconductor device structure

Assignees

• Vaid Alok
• Saleh Ned R
• Sendelbach Matthew J
• Rana Narender N
• Globalfoundries Inc
• IBM

Inventors

• Vaid Alok
• Saleh Ned R
• Sendelbach Matthew J
• Rana Narender N

Classifications

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10P74/203 Primary

  Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects · CPC title

• G03F7/70625

  Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness · CPC title

• H01L22/20

  Electricity · mapped topic

• H01L22/12 Primary

  Electricity · mapped topic