High speed level translator

Patent metadata

Field	Value
Publication number	US-9871523-B2
Application number	US-201615244829-A
Country	US
Kind code	B2
Filing date	Aug 23, 2016
Priority date	Aug 19, 2014
Publication date	Jan 16, 2018
Grant date	Jan 16, 2018

Abstract

A high speed VPP level translator circuit using thin-oxide field effect transistors (FETs) and methods of use are disclosed. The level translator includes a resistor divider and a one-shot circuit in parallel with the resistor divider. The one-shot circuit conducts to assist a transition from a first state to a second state, and is non-conducting during the transition from the second state to the first state.

First claim

What is claimed:

1. A level translator, comprising:
a resistor divider configured to be switched on/off to provide an output of a low voltage and a high voltage; and
a one-shot circuit coupled to the output and comprised of an inverter chain and a pull-up stack of transistors in parallel with the resistor divider coupled to receive an input signal oscillating between a voltage Vdd and a ground, the one-shot circuit conducting for a transition from a first state to a second state through a conduction path provided by the pull-up stack, and non-conducting for an opposite transition,
wherein the one-shot circuit translates from the low voltage to the high voltage using the transistors arranged in parallel with a first resistor of the resistor divider and the inverter chain having outputs controlling gates of the transistors to generate an output signal oscillating between a voltage VPP2 and VPP to provide a conduction path between an output level of the first resistor for operation between voltage levels with which the Vdd and the ground can be translated to VPP2 and VPP.

2. The level translator of claim 1 , wherein the transistors of the one-shot circuit are provided with a feedback loop to improve switching performance in a direction serviced by a resistor pull up.

3. The level translator of claim 1 , wherein a 4-level translator circuit translates input signals from Gnd/Vdd to output levels VPP2/VPP where FET voltage stress is limited to Vdd level.

4. The level translator of claim 1 , wherein the resistor divider comprises the first resistor R 0 and a second resistor R 1 , in series, which is enabled by transistors T 0 and T 1 , the transistor T 1 is a series stack device to limit stress across transistor T 0 to Vdd.

5. The level translator of claim 4 , wherein resistive values of the resistors R 0 and R 1 are chosen to output voltage signal V 2 IN of approximately VPP2 when the transistor T 0 receives a Vdd level logic input signal, and when the resistor divider is disabled, the voltage signal V 2 IN is approximately VPP.

6. The level translator of claim 5 , wherein:
the one-shot circuit comprises a pull-up stack comprising two transistors T 2 and T 3 , in series, which allows conduction from VPP to V 2 IN;
the pull-up stack is enabled during transition of low-to-high switching which increases switching speed; and
the pull-up stack is disabled when low-to-high switching is complete such that a subsequent high-to low transition is unimpeded by the pull-up stack.

7. The level translator of claim 6 , wherein the inverter chain comprises inverters.

8. The level translator of claim 7 , wherein the inverters are connected in series to establish a pull-up gate signal and its complement to the transistors T 2 and T 3 .

9. The level translator of claim 8 , wherein the transistors are thin-oxide FETs.

10. The level translator of claim 9 , wherein the thin-oxide FETs improve a timing alignment to Vdd-level clocks.

11. The level translator of claim 9 , wherein the Vdd is 1.05V and the VPP is 1.6V.

12. A level translator, comprising:
a resistor divider comprising a first resistor R 0 and a second resistor R 1 , in series, which is enabled by transistors T 0 and T 1 , the transistor T 1 is a series stack device to limit stress across transistor T 0 to Vdd; and
a one-shot circuit in parallel with the resistor divider and comprising a pull-up stack comprising two transistors T 2 and T 3 , in series, which allows conduction from VPP to V 2 IN to assist a transition from a first state to a second state, and is non-conducting during the transition from the second state to the first state,
wherein
resistive values of the resistors R 0 and R 1 are chosen to output voltage signal V 2 IN of approximately VPP2 when the transistor T 0 receives a Vdd level logic input signal, and when the resistor divider is disabled, the voltage signal V 2 IN is approximately VPP, and
the pull-up stack is enabled during transition of low-to-high switching which increases switching speed and is disabled when low-to-high switching is complete such that a subsequent high-to low transition is unimpeded by the pull-up stack.

13. The level translator of claim 12 , wherein the one-shot circuit further comprises an inverter chain comprising inverters.

14. The level translator of claim 13 , wherein the inverters are connected in series to establish a pull-up gate signal and its complement to the transistors T 2 and T 3 .

Assignees

• IBM

Inventors

• Fifield John A

Classifications

• H03K19/0944

  using MOSFET {or insulated gate field-effect transistors, i.e. IGFET}(H03K19/096 takes precedence) · CPC title

• H03K19/01855 Primary

  synchronous, i.e. using clock signals · CPC title

• H03K19/01742

  by means of a pull-up or down element · CPC title