Semiconductor device and method of forming the same

Patent metadata

Field	Value
Publication number	US-10608094-B2
Application number	US-201815877395-A
Country	US
Kind code	B2
Filing date	Jan 23, 2018
Priority date	Jan 23, 2018
Publication date	Mar 31, 2020
Grant date	Mar 31, 2020

Abstract

Semiconductor devices and methods of forming the same are disclosed. A semiconductor device includes a substrate, a gate structure over the substrate, a spacer and a source/drain region. The gate structure is disposed over the substrate. The spacer is disposed on a sidewall of the gate structure, wherein the spacer has a top surface lower than a top surface of the gate structure. The source/drain region is disposed adjacent to a sidewall of the spacer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a gate structure over the substrate;
a spacer on a sidewall of the gate structure, wherein the spacer has a top surface lower than a top surface of the gate structure; and
a raised source/drain region protruding from the substrate, wherein the spacer has a top portion and a bottom portion integrally formed with the top portion, the bottom portion is disposed between and in physical contact with the gate structure and the raised source/drain region, and the top portion is protruded from the raised source/drain region.

2. The semiconductor device of claim 1 , wherein the gate structure comprises a gate electrode, and the top surface of the spacer is lower than a top surface of the gate electrode.

3. The semiconductor device of claim 1 , wherein the top portion of the spacer has a curved outer sidewall.

4. The semiconductor device of claim 1 , wherein the top portion of the spacer has a tapered outer sidewall.

5. The semiconductor device of claim 1 , wherein the top portion of the spacer has a first part with a substantially vertical outer sidewall and a second part with a tapered outer sidewall, and the second part is disposed between the first part and the bottom portion.

6. The semiconductor device of claim 5 , wherein the first part has a substantially horizontal top surface physically connecting the substantially vertical outer sidewall of the first part.

7. The semiconductor device of claim 1 , further comprising a dielectric layer covering the spacer, and an outer sidewall of the top portion of the spacer is in physical contact with the dielectric layer.

8. A semiconductor device, comprising:
a substrate;
a gate structure over the substrate;
a single-layer spacer on a sidewall of the gate structure, wherein a portion of the sidewall of the gate structure is not covered by the single-layer spacer; and
a raised source/drain region protruding from the substrate, wherein the single-layer spacer is in physical contact with the gate structure and the raised source/drain region.

9. The semiconductor device of claim 8 further comprising a contact etch stop layer (CESL) over the substrate, wherein the CESL is in physical contact with the portion of the sidewall of the gate structure and an outer sidewall of the single-layer spacer.

10. The semiconductor device of claim 9 , wherein a top surface of the CESL is leveled with a top surface of the gate structure.

11. The semiconductor device of claim 8 , wherein an outer sidewall of the single-layer spacer has a first endpoint on the sidewall of the gate structure and a second endpoint on the raised source/drain region.

12. The semiconductor device of claim 8 , wherein the single-layer spacer has a curved outer sidewall.

13. A method of forming a semiconductor device, comprising:
providing a substrate;
forming a gate structure over the substrate;
forming a spacer adjacent to a sidewall of the gate structure;
forming a source/drain region aside the gate structure;
partially removing the spacer, to reduce a height of the spacer; and
after partially removing the spacer, sharping an outer sidewall of the spacer.

14. The method of claim 13 , wherein an outer sidewall of the spacer is curved after partially removed.

15. The method of claim 13 , wherein after sharping, the outer sidewall has a substantially vertical sidewall and a tapered sidewall.

16. The method of claim 13 , wherein the gate structure comprises a gate electrode, and a top surface of the spacer is lower than a top surface of the gate electrode.

17. The method of claim 13 , wherein a top of the spacer is substantially flush with a top of the gate structure.

18. The method of claim 13 , wherein partially removing the spacer is performed after forming the source/drain region.

19. The method of claim 13 , wherein the spacer has a top portion and a bottom portion integrally formed with the top portion, the bottom portion is disposed between and in physical contact with the gate structure and the source/drain region, and the top portion is protruded from the source/drain region.

20. The method of claim 13 , wherein after sharping, the outer sidewall is tapered.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsai Fu-Tsun
• Chen I-Chih
• Huang Chih-Mu
• Huang Jiun-Jie
• Wang Jen-Pan

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H01L29/66795

  Electricity · mapped topic

• H01L21/3065

  Electricity · mapped topic

• H01L29/42368 Primary

  Electricity · mapped topic