CDAC (capacitive DAC (digital-to-analog converter)) unit cell for multiphase RFDAC (radio frequency DAC)

Patent metadata

Field	Value
Publication number	US-10601437-B1
Application number	US-201816233450-A
Country	US
Kind code	B1
Filing date	Dec 27, 2018
Priority date	Dec 27, 2018
Publication date	Mar 24, 2020
Grant date	Mar 24, 2020

Abstract

CDAC (Capacitive DAC (Digital-to-Analog Converter) unit cells and RFDACs (Radio Frequency DACs) employing such CDAC unit cells are disclosed that can be employed for mmWave (millimeter wave) communication are disclosed. One example CDAC unit cell comprises: four capacitors connected in pairs to two differential outputs of the CDAC unit cell; and four logic gates, wherein each logic gate of the four logic gates is configured to receive an associated clock signal of four different clock signals and an associated enable signal of four different enable signals, and wherein each logic gate of the four logic gates is configured to trigger an associated pulse from an associated capacitor of the four capacitors based on the associated clock signal and the associated enable signal of that logic gate.

First claim

What is claimed is:

1. A CDAC (Capacitive DAC (Digital-to-Analog Converter)) unit cell, comprising:
a first capacitor configured to generate a first pulse to a first differential output of the CDAC unit cell in response to a first trigger signal, wherein the first trigger signal is generated based on a first enable signal and a first clock signal;
a second capacitor configured to generate a second pulse to the first differential output of the CDAC unit cell in response to a second trigger signal, wherein the second trigger signal is generated based on a second enable signal and a second clock signal;
a third capacitor configured to generate a third pulse to a second differential output of the CDAC unit cell in response to a third trigger signal, wherein the third trigger signal is generated based on a third enable signal and a third clock signal, and wherein the first differential output is different from the second differential output;
a fourth capacitor configured to generate a fourth pulse to the second differential output of the CDAC unit cell in response to a fourth trigger signal, wherein the fourth trigger signal is generated based on a fourth enable signal and a fourth clock signal;
a first logic gate configured to receive the first enable signal and the first clock signal, and to generate the first trigger signal based on the first enable signal and the first clock signal;
a second logic gate configured to receive the second enable signal and the second clock signal, and to generate the second trigger signal based on the second enable signal and the second clock signal;
a third logic gate configured to receive the third enable signal and the third clock signal, and to generate the third trigger signal based on the third enable signal and the third clock signal; and
a fourth logic gate configured to receive the fourth enable signal and the fourth clock signal, and to generate the fourth trigger signal based on the fourth enable signal and the fourth clock signal, and
wherein each of the first enable signal, the second enable signal, the third enable signal, and the fourth enable signal is different, and wherein each of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal is different.

2. The CDAC unit cell of claim 1 , wherein the first logic gate and the fourth logic gate are a first type of logic gate, and the second logic gate and the third logic gate are a second type of logic gate, wherein the first type of logic gate is different than the second type of logic gate.

3. The CDAC unit cell of claim 1 , further comprising:
a first inverter, wherein the first capacitor is configured to receive the first trigger signal via the first inverter;
a second inverter, wherein the second capacitor is configured to receive the second trigger signal via the second inverter;
a third inverter, wherein the third capacitor is configured to receive the third trigger signal via the third inverter; and
a fourth inverter, wherein the fourth capacitor is configured to receive the fourth trigger signal via the fourth inverter.

4. A RFDAC (Radio Frequency DAC (Digital-to-Analog Converter)) comprising:
a DAC array comprising a plurality of CDAC (Capacitive DAC) unit cells arranged in a plurality of lines and a plurality of columns, wherein each CDAC unit cell of the plurality of CDAC unit cells comprises:
a first capacitor of that CDAC unit cell configured to generate a first pulse to a first differential output of that CDAC unit cell in response to a first trigger signal of that CDAC unit cell, wherein the first trigger signal of that CDAC unit cell is generated based on a first enable signal of that CDAC unit cell and a first clock signal of that CDAC unit cell;
a second capacitor of that CDAC unit cell configured to generate a second pulse to the first differential output of that CDAC unit cell in response to a second trigger signal of that CDAC unit cell, wherein the second trigger signal of that CDAC unit cell is generated based on a second enable signal of that CDAC unit cell and a second clock signal of that CDAC unit cell;
a third capacitor of that CDAC unit cell configured to generate a third pulse to a second differential output of that CDAC unit cell in response to a third trigger signal of that CDAC unit cell, wherein the third trigger signal of that CDAC unit cell is generated based on a third enable signal of that CDAC unit cell and a third clock signal of that CDAC unit cell, wherein the first differential output is different from the second differential output; and
a fourth capacitor of that CDAC unit cell configured to generate a fourth pulse to the second differential output of that CDAC unit cell in response to a fourth trigger signal of that CDAC unit cell, wherein the fourth trigger signal of that CDAC unit cell is generated based on a fourth enable signal of that CDAC unit cell and a fourth clock signal of that CDAC unit cell,

wherein each of the first enable signal of that CDAC unit cell, the second enable signal of that CDAC unit cell, the third enable signal of that CDAC unit cell, and the fourth enable signal of that CDAC unit cell is different, and wherein each of the first clock signal of that CDAC unit cell, the second clock signal of that CDAC unit cell, the third clock signal of that CDAC unit cell, and the fourth clock signal of that CDAC unit cell is different,
wherein the plurality of columns comprises a plurality of even columns comprising a first set of CDAC unit cells of the plurality of CDAC unit cells and the plurality of columns comprises a plurality of odd columns comprising a second set of CDAC unit cells of the plurality of CDAC unit cells, and
wherein, for at least one phase transition from a first phase to a second phase, the first set of CDAC unit cells is configured to generate an associated pulse for the first phase and the second set of CDAC unit cells is configured to generate an associated pulse for the second phase.

5. The RFDAC of claim 4 , wherein each CDAC unit cell of the plurality of CDAC unit cells comprises:
a first logic gate of that CDAC unit cell configured to receive the first enable signal of that CDAC unit cell and the first clock signal of that CDAC unit cell, and to generate the first trigger signal of that CDAC unit cell based on the first enable signal of that CDAC unit cell and the first clock signal of that CDAC unit cell;
a second logic gate of that CDAC unit cell configured to receive the second enable signal of that CDAC unit cell and the second clock signal of that CDAC unit cell, and to generate the second trigger of that CDAC unit cell signal based on the second enable signal of that CDAC unit cell and the second clock signal of that CDAC unit cell;
a third logic gate of that CDAC unit cell configured to receive the third enable signal of that CDAC unit cell and the third clock signal of that CDAC unit cell, and to generate the third trigger signal of that CDAC unit cell based on the third enable signal of that CDAC unit cell and the third clock signal of that CDAC unit cell; and
a fourth logic gate of that CDAC unit cell configured to receive the fourth enable signal of that CDAC unit cell and the fourth clock signal of that CDAC unit cell, and to generate the fourth trigger signal of that CDAC unit cell based on the fourth enable signal of that CDAC unit cell and the fourth clock signal of that CDAC unit cell.

6. The RFDAC of claim 5 , wherein, for each CDAC unit cell, the first logic gate of that CDAC unit cell and the fourth logic gate of that CDAC unit cell are a first type of logic gate, and the second logic gate of that CDAC unit cell and the third logic gate of that CDAC unit cell are a second type of logic gate, wherein the first type of logic gate is di

Assignees

• Intel Corp

Inventors

• Kuttner Franz

Classifications

• H03M1/804 Primary

  with charge redistribution · CPC title

• H04B1/04

  Circuits · CPC title

• H03M1/661

  Improving the reconstruction of the analogue output signal beyond the resolution of the digital input signal, e.g. by interpolation, by curve-fitting, by smoothing · CPC title

• H04B1/44

  Transmit/receive switching · CPC title

• H03M1/86

  with intermediate conversion to frequency of pulses · CPC title