Digital to Analog Converter Cell for Signed Operation

Patent metadata

Field	Value
Publication number	US-2016173269-A1
Application number	US-201414571531-A
Country	US
Kind code	A1
Filing date	Dec 16, 2014
Priority date	Dec 16, 2014
Publication date	Jun 16, 2016
Grant date	—

Abstract

A communication system receives an inputs signal and generates a converted output signal. A control signal selectively activates one or more source cells among an array of cells. The selected source cells generate a first charge package and a second charge package at a cell output terminal for the array of cells to generate the converted output signal. The first charge package and the second charge package are generated during the same clock cycle.

First claim

1 . A communication system comprising:
an input terminal configured to receive an input signal; a converter comprising an array of source cells configured to generate an output at an output terminal; and a decoding component configured to generate a control signal that selectively activates at least one source cell of the array of source cells to generate the output based on the input signal; wherein the at least one source cell comprises a source cell, configured to generate a first charge package and a second charge package corresponding to a data cycle, comprising a first capacitor and a second capacitor coupled to a cell output terminal, the first capacitor configured to generate the first charge package and the second capacitor configured to generate the second charge package.

2 . (canceled)

3 . The communication system of claim 1 , further comprising:
a local oscillator configured to generate a local oscillator signal as the data cycle to generate the output at the output terminal, wherein the at least one source cell comprises a corresponding cell output terminal selectively coupled to the output terminal based on the control signal.

4 . A communication system comprising:
an input terminal configured to receive an input signal; a converter comprising an array of source cells configured to generate an output at an output terminal; a decoding component configured to generate a control signal that selectively activates at least one source cell of the array of source cells to generate the output based on the input signal, wherein a source cell of the at least one source cell is configured to generate a first charge package and a second charge package corresponding to a data cycle; and a sign component configured to generate a bipolar sign operation with the output via the source cell by shifting the first charge package and the second charge package as a function of time.

5 . The communication system of claim 1 , wherein the source cell comprises a first signal branch driven by a clock signal of a local oscillator and a second signal branch driven by an inverted clock signal of the local oscillator.

6 . The communication system of claim 5 , wherein the first signal branch comprises a first driver component and the first capacitor configured to generate the first charge package and the second signal branch comprises a second driver component and the second capacitor configured to generate the second charge package.

7 . The communication system of claim 5 , wherein the first signal branch is configured to generate the first charge package at a cell output terminal in response to a first edge of a local oscillator signal and the second signal branch is configured to generate the second charge package at the cell output terminal in response to a second edge of the local oscillator signal that is opposite to the first edge.

8 . The communication system of claim 1 , wherein the source cell is further configured to alter an output power of the source cell by changing a supply voltage to the first capacitor and the second capacitor, and increase an operational bandwidth by switching to a tri-state mode of operation by altering an impedance of the source cell based on a state of a set of switches.

9 . A digital to analog converter comprising:
a digital input terminal configured to receive a digital input word; an array of source cells that comprise:
a cell output terminal;
a first charge branch configured to provide a first charge source to the cell output terminal during a clock cycle; and
a second charge branch configured to provide a second charge source to the cell output terminal during the clock cycle;
wherein the first charge branch comprises a first capacitor coupled to a positive supply voltage and the second charge branch comprise a second capacitor coupled to a negative supply voltage; and
a decoder component configured to generate a control word based on a digital input and selectively couple and activate at least one source cell of the array of source cells to an output terminal based on the control word.

10 . The digital to analog converter of claim 9 , wherein the decoder component is further configured to generate a first cell output and a second cell output at the cell output terminal of the at least one source cell, wherein the first cell output is inverted with respect to the second cell output.

11 . The digital to analog converter of claim 9 , wherein the decoder component is configured to generate a first sign operation via the first charge branch and the second charge branch of the at least one source cell, and generate a second sign operation that is different than the first sign operation via the first charge branch and the second charge branch based on a shift in time of the first charge source and the second charge source.

12 . (canceled)

13 . The digital to analog converter of claim 9 , wherein the first charge branch and the second charge branch comprise an output stage supply component configured to alter a supply voltage to the first capacitor of the first charge branch and the second capacitor of the second charge branch.

14 . The digital to analog converter of claim 9 , further comprising a tuning component configured to tune the first capacitor of the first charge branch and the second capacitor of the second charge branch by changing an impedance of a driver stage of the first charge branch and the second charge branch.

15 . The digital to analog converter of claim 9 , wherein the first charge branch is configured to generate the first charge source at a first local oscillator edge and the second charge branch is configured to generate the second charge source at second oscillator edge that comprises an opposite polarity than the first local oscillator edge.

16 . A digital to analog converter comprising:
a digital input terminal configured to receive a digital input word; an array of source cells that comprise:
a cell output terminal;
a first charge branch configured to provide a first charge source to the cell output terminal during a clock cycle; and
a second charge branch configured to provide a second charge source to the cell output terminal during the clock cycle;
a decoder component configured to generate a control word based on a digital input and selectively couple and activate at least one source cell of the array of source cells to an output terminal based on the control word; and a tuning component configured to increase a bandwidth range of the array of source cells by changing an impedance of a driver stage of the first charge branch and the second charge branch.

17 . A digital to analog converter comprising:
a digital input terminal configured to receive a digital input word; an array of source cells that comprise:
a cell output terminal;
a first charge branch configured to provide a first charge source to the cell output terminal during a clock cycle;
a second charge branch configured to provide a second charge source to the cell output terminal during the clock cycle, wherein the first charge branch comprises a first capacitor having a first capacitance and the second charge branch comprises a second capacitor having a second capacitance that is substantially equal to the first capacitance; and
a decoder component configured to generate a control word based on a digital input and selectively couple and activate at least one source cell of the array of source cells to an output terminal based on the control word.

18 . A method of a digital to analog converter com

Assignees

• Intel Corp

Inventors

• Kuttner Franz
• Fulde Michael

Classifications

• H04L1/22

  using redundant apparatus to increase reliability · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H04L7/0083 Primary

  taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks · CPC title

• H03M1/068 Primary

  the original and additional components or elements being complementary to each other, e.g. CMOS · CPC title

• H03M1/0863

  of switching transients, e.g. glitches · CPC title