Digital to analog converter with passive reconstruction filter

Patent metadata

Field	Value
Publication number	US-9900022-B2
Application number	US-201715408396-A
Country	US
Kind code	B2
Filing date	Jan 17, 2017
Priority date	Jan 15, 2016
Publication date	Feb 20, 2018
Grant date	Feb 20, 2018

Abstract

DAC design uses a passive reconstruction filter. The reconstruction filter includes a notch filter and series peaking filter. The notch filter provides notch filtering at the DAC clock frequency. The peaking filter increases signal bandwidth while attenuating frequency content at harmonics of the DAC clock frequency. The notch filter can be an LC notch filter with a notch inductor Ln and a notch capacitor Cn. The peaking filter can be a series peaking inductor Ls (shunted with a filter capacitor Cp). In a differential configuration, the passive reconstruction filter can be ±LC notch filters (with ±Ln notch inductors), and the peaking filter can be ±Ls peaking inductors coupled in series to the ±LC notch filters. The ±Ln notch inductors, ±Ls peaking inductors can be mutually wound as single inductors. For an example direct conversion RF transmit chain, IQ± signal paths are implemented with differential DAC designs including passive reconstruction filters.

First claim

The invention claimed is:

1. A circuit for analog to digital signal conversion, comprising
a digital-to-analog converter (DAC) coupled to receive at an input an input digital data signal, to convert the digital data signal to a DAC output signal;
a reconstruction filter to filter the DAC output signal, including
at least one notch filter to provide notch filtering, and
a peaking filter coupled in series with the notch filter,

the reconstruction filter providing a filtered DAC output signal that is band limited.

2. The circuit of claim 1 , wherein
the notch filter comprises an LC notch filter with at least one notch inductor Ln and at least one notch capacitor Cn.

3. The circuit of claim 2 , wherein
the DAC comprises a differential DAC to convert the input digital data signal into differential DAC output signals at +DAC and −DAC outputs;
the notch filter comprises a +LC notch filter coupled between the +DAC output and a circuit common, and a −LC notch filter coupled between the −DAC output and the circuit common; and
the peaking circuit comprises a peaking inductor +Ls coupled to the +LC notch filter, and a peaking inductor −Ls coupled to the −LC notch filter.

4. The circuit of claim 3 ,
wherein the ±LC notch filters respectively include ±Ln inductors, and the peaking circuit includes ±Ls inductors; and
wherein the ±Ln notch inductors and the ±Ls peaking inductors are respectively mutually wound as single inductors.

5. The circuit of claim 3 , adapted for use in a direct conversion RF transmit signal chain including an IQ± signal paths I-Path and Q-Path:
wherein the I-Path includes an I-Path differential DAC and an I-Path reconstruction filter providing filtered I-Path differential DAC outputs I±; and
wherein the Q-Path includes a Q-Path differential DAC and Q-Path reconstruction filter providing filtered Q-Path differential DAC outputs Q±.

6. The circuit of claim 3 , wherein the peaking circuit further includes filter capacitors Cp coupled respectively between the peaking inductors ±Ls and a circuit common.

7. The circuit of claim 1 , wherein the DAC and the reconstruction filter are integrated into a single integrated circuit.

8. The circuit of claim 1 , wherein the at least one notch filter is connected to the DAC, and the peaking circuit is connected to the at least one notch filter, and outputs the filtered DAC output signal.

9. A DAC (digital-to-analog conversion) circuit for use in an RF (radio frequency) transmitter, comprising
a digital-to-analog converter (DAC) coupled to receive an input digital data signal, to convert the digital data signal to a DAC RF signal;
a reconstruction filter to filter the DAC RF signal, including
at least one notch filter to provide notch filtering, and
a peaking filter coupled in series with the notch filter,

the reconstruction filter providing a filtered DAC RF signal that is band limited.

10. The DAC circuit of claim 9 , wherein
the notch filter comprises an LC notch filter with at least one notch inductor Ln and at least one notch capacitor Cn.

11. The DAC circuit of claim 10 , wherein
the DAC comprises a differential DAC to convert the input digital data signal into differential DAC RF signals at +DAC and −DAC outputs;
the notch filter comprises a ±LC notch filter coupled between the +DAC output and a circuit common, and a −LC notch filter coupled between the −DAC output and the circuit common; and
the peaking circuit comprises a peaking inductor ±Ls coupled to the ±LC notch filter, and a peaking inductor −Ls coupled to the −LC notch filter.

12. The DAC circuit of claim 11 ,
wherein the ±LC notch filters respectively include ±Ln inductors; and
the peaking circuit includes ±Ls inductors; and
wherein the ±Ln notch inductors and the ±Ls peaking inductors are respectively mutually wound as single inductors.

13. The circuit of claim 11 , wherein the peaking circuit further includes filter capacitors Cp coupled respectively between the peaking inductors ±Ls and a circuit common.

14. The DAC circuit of claim 11 , adapted for use in a direct conversion RF transmit signal chain including an IQ± signal paths I-Path and Q-Path:
wherein the I-Path includes an I-Path differential DAC and an I-Path reconstruction filter providing filtered I-Path differential DAC outputs I±; and
wherein the Q-Path includes a Q-Path differential DAC and Q-Path reconstruction filter providing filtered Q-Path differential DAC outputs Q±.

15. The DAC circuit of claim 14 , wherein, for both the I-Path and the Q-Path, the reconstruction filter comprises:
±LC notch filters with ±Ln inductors; and
the peaking circuit including ±Ls inductors; and
the ±Ln notch inductors and the ±Ls peaking inductors are respectively mutually wound as single inductors.

16. The DAC circuit of claim 15 , wherein the peaking circuit further includes filter capacitors Cp coupled respectively between the peaking inductors ±Ls and a circuit common.

17. The DAC circuit of claim 9 , wherein the at least one notch filter is connected to the DAC, and the peaking circuit is connected to the at least one notch filter, and outputs the filtered DAC RFsignal.

18. The DAC circuit of claim 9 , wherein the DAC and the reconstruction filter are integrated into a single integrated circuit.

19. A method of digital-to-analog conversion for use in an RF (radio frequency) transmit (TX) signal chain, the method comprising
converting an input digital data signal to a DAC RF signal;
reconstruction filtering the DAC RF signal, by
notch filtering the DAC RF signal with a notch filter an LC notch filter with at least one notch inductor Ln and at least one notch capacitor Cn, and
filtering the notch filtered output of the notch filter with a peaking filter including a peak filtering inductor Ls to provide a filtered DAC RF signal that is band limited.

20. The method of claim 19 , wherein:
the input digital data signal is converted to differential DAC RF signals at +DAC and −DAC outputs; and
reconstruction filtering is performed with
a notch filter that includes a +LC notch filter coupled between the +DAC output and a circuit common, and a −LC notch filter coupled between the −DAC output and the circuit common, and
a peaking circuit that includes a peaking inductor +Ls coupled to the +LC notch filter, and a peaking inductor −Ls coupled to the −LC notch filter.

Assignees

• Texas Instruments Inc

Inventors

• Ghosh Diptendu
• Litmanen Petteri Matti
• Akhtar Siraj

Classifications

• H03M1/661 Primary

  Improving the reconstruction of the analogue output signal beyond the resolution of the digital input signal, e.g. by interpolation, by curve-fitting, by smoothing · CPC title

• H03H7/0115 Primary

  comprising only inductors and capacitors (H03H7/075, H03H7/09, H03H7/12, H03H7/13 take precedence) · CPC title

• H03M1/0631 Primary

  Smoothing · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title