Integrated high-side driver for P-N bimodal power device

Patent metadata

Field	Value
Publication number	US-10601422-B2
Application number	US-201715809291-A
Country	US
Kind code	B2
Filing date	Nov 10, 2017
Priority date	Mar 11, 2016
Publication date	Mar 24, 2020
Grant date	Mar 24, 2020

Abstract

An integrated circuit chip includes a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having an N-gate coupled to receive an input signal and a level shifter coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device. A method of operating an N-P-LDMOS power device is also disclosed.

First claim

What is claimed is:

1. An integrated circuit comprising:
a circuit input, a circuit drain, and a circuit source;
a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (N-P-LDMOS) device having a NMOS transistor, a PMOS transistor, and a drain bond pad region, the NMOS transistor having a gate, a drain, and a source, the PMOS transistor having a gate, a drain, and a source, the gate of the NMOS transistor being coupled to the circuit input, the drain of the NMOS being coupled to the circuit drain and the source of the PMOS transistor, and the source of the NMOS transistor being coupled to the circuit source and the drain of the PMOS transistor;
a level shifter having an input coupled to the circuit input and an output, the level shifter including an N LDMOS transistor having a gate coupled to the circuit input, having a drain, and having a source;
a P-gate driver having an input coupled to the output of the level shifter and having an output coupled to the gate of the PMOS transistor, the P-gate driver being integrated in the drain bond pad region.

2. The integrated circuit of claim 1 in which the P-gate driver includes a resistor coupled between the drain of the N LDMOS transistor and the circuit drain of the N-P-LDMOS device and includes a diode coupled between the drain of the N LDMOS transistor and the circuit drain of the N-P-LDMOS device.

3. The integrated circuit of claim 2 in which the gate of the PMOS transistor is coupled to between the resistor and the N LDMOS transistor.

4. The integrated circuit of claim 3 including a current source coupled between the source of the N-LDMOS transistor and a voltage VSS.

5. The integrated circuit of claim 4 in which the current source is separate from the integrated circuit.

6. The integrated circuit of claim 4 in which the voltage VSS is a negative voltage.

7. The integrated circuit of claim 3 in which the N LDMOS transistor is embedded in the bimodal power N-P-LDMOS device and isolated from the bimodal power N-P-LDMOS device by a given voltage.

8. The integrated circuit of claim 7 in which the given voltage is 20 volts.

9. An integrated circuit comprising:
a gate terminal; a drain terminal; a source terminal; a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having an N-gate and a P-gate, the N-P-LDMOS device being coupled between the drain terminal and the source terminal and the N-gate of the N-P-LDMOS device being coupled to the gate terminal; a level shifter including an N-LDMOS transistor having a gate coupled to the gate terminal, having a drain, and having a source;
a P-gate driver coupled between the N-LDMOS transistor and the P-gate; and
an N-gate driver coupled between the gate terminal and the N-gate.

10. The integrated circuit of claim 9 , in which the N-P-LDMOS device includes a NMOS transistor and a PMOS transistor, the NMOS transistor having a drain and a source and the PMOS transistor having a drain and a source, the drain terminal is coupled to the drain of the NMOS transistor and the source of the PMOS transistor, and the source terminal is coupled to the source of the NMOS transistor and the drain of the PMOS transistor.

11. The integrated circuit of claim 9 , in which the P-gate driver is integrated in a drain bond pad region of the N-P-LDMOS device.

12. The integrated circuit of claim 9 , wherein the P-gate driver includes a resistor, having first and second terminals, coupled between the drain terminal and the drain of the N-LDMOS transistor, and a diode coupled between the first and second terminals of the resistor.

13. The integrated circuit of claim 12 , in which the N-LDMOS transistor is embedded in the bimodal power N-P-LDMOS device and isolated from the bimodal power N-P-LDMOS device by a given voltage.

14. The integrated circuit of claim 13 , in which the given voltage is 20 volts.

15. The integrated circuit of claim 12 , in which the P-gate is coupled to between the resistor and the N LDMOS transistor.

Assignees

• Texas Instruments Inc

Inventors

• Zhang Yongxi
• Pendharkar Sameer P
• Hower Philip L
• Giombanco Salvatore
• Marino Filippo
• Sridhar Seetharaman

Classifications

• H03K19/018521 Primary

  of complementary type, e.g. CMOS · CPC title

• H03K17/122

  in field-effect transistor switches · CPC title

• H01L29/0696

  Electricity · mapped topic

• H01L29/7835

  Electricity · mapped topic

• H01L21/823814

  Electricity · mapped topic