Integrated high-side driver for P-N bimodal power device

Patent metadata

Field	Value
Publication number	US-9843322-B2
Application number	US-201615067928-A
Country	US
Kind code	B2
Filing date	Mar 11, 2016
Priority date	Mar 11, 2016
Publication date	Dec 12, 2017
Grant date	Dec 12, 2017

Abstract

An integrated circuit chip includes a bimodal power N-P-Laterally Diffused Metal Oxide Semiconductor (LDMOS) device having an N-gate coupled to receive an input signal and a level shifter coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device. A method of operating an N-P-LDMOS power device is also disclosed.

First claim

What is claimed is:

1. An N-P-Lateral Double-Diffused Metal-Oxide-Semiconductor (LDMOS) device and control circuit formed on a single chip, the N-P-LDMOS device and control circuit comprising:
a source and an N-gate for the N-P-LDMOS device that form an outer loop comprising first fingers, the first fingers extending inward from the outer loop, and a first gap between first and second ends of the outer loop, the first gap being positioned opposite the first fingers;
a drain and a P-gate for the N-P-LDMOS device that form an inner loop that is enclosed within the outer loop, the inner loop comprising second fingers that extend outward from the inner loop to form conduction channels between the second fingers of the inner loop and the first fingers of the outer loop, the inner loop further comprising a second gap between first and second ends of the inner loop, the second gap being positioned opposite the second fingers; and
an N-LDMOS transistor comprising a source and an N-gate located in the first gap and a drain located in the second gap, wherein the drain of the N-LDMOS transistor is coupled to a P-gate bond pad of the N-P-LDMOS device that is located within the inner loop, the N-gate of the N-LDMOS transistor is coupled to receive a signal input to control the N-gate of the N-P-LDMOS device and the source of the N-LDMOS transistor is coupled to one of a lower rail and a negative voltage.

2. The N-P-LDMOS device and control circuit as recited in claim 1 wherein the N-gate of the N-P-LDMOS device is coupled to receive an input signal and the N-LDMOS transistor is coupled to receive the input signal and to provide a control signal to a P-gate driver of the N-P-LDMOS device.

3. The IC chip as recited in claim 2 wherein the input signal is a low-voltage signal and the control signal is a high voltage signal.

4. The IC chip as recited in claim 3 wherein the P-gate driver is integrated in a drain bond pad region of the N-P-LDMOS device.

5. The IC chip as recited in claim 4 wherein the P-gate driver comprises a resistor coupled between the drain of the N LDMOS transistor and a drain of the N-P-LDMOS device and a diode coupled between first and second terminals of the resistor.

6. The IC chip as recited in claim 5 wherein the P-gate of the N-P-LDMOS device is coupled to a point between the resistor and the N-LDMOS transistor.

7. The IC chip as recited in claim 6 wherein a current source is coupled between the source of the N-LDMOS transistor and VSS.

8. The IC chip as recited in claim 7 wherein the current source is off-chip.

9. The IC chip as recited in claim 7 wherein VSS is a negative voltage.

10. The IC chip as recited in claim 6 wherein the N-LDMOS transistor is isolated from the N-P-LDMOS device by a given voltage.

11. The IC chip as recited in claim 10 wherein the given voltage is 20 volts.

12. The N-P-LDMOS device and control circuit as recited in claim 1 wherein the P-gate bond pad is further coupled to a drain bond pad of the N-P-LDMOS device through a resistor formed within the inner loop.

13. The N-P-LDMOS device and control circuit as recited in claim 12 wherein the P-gate bond pad is further coupled to the bond drain pad of the N-P-LDMOS device through a diode formed within the inner loop.

14. The N-P-LDMOS device and control circuit as recited in claim 13 wherein the source of the N-LDMOS transistor is coupled to the one of the lower rail and the negative voltage through a current source.

15. The N-P-LDMOS device and control circuit as recited in claim 1 , the N-P-LDMOS device and control circuit further comprising:
a bottom n-type region formed on a p-type substrate;
a top n-type region overlying the bottom n-type region, a portion of the bottom n-type region and the top n-type region being separated by a buried p-type region;
a second p-type region partially overlying the top n-type region;
an n-type well that is formed adjacent a first end of the second p-type region and the top n-type region, the n-type well containing a first heavily-doped n-type region and a first heavily doped p-type region, the first heavily doped n-type region and the first heavily-doped p-type region being coupled to a drain electrode of the N-P-LDMOS device;
a p-type well that is formed adjacent a second end of the second p-type region and the top n-type region, the p-type well containing a second heavily-doped n-type region and a second heavily doped p-type region, the second heavily doped n-type region and the second heavily-doped p-type region being coupled to a source electrode of the N-P-LDMOS device;
the P-gate of the N-P-LDMOS device overlying a portion of the first heavily-doped p-type region, the n-type well and a portion of the second p-type region; and
the N-gate of the N-P-LDMOS device overlying a portion of the second heavily-doped n-type region, the p-type well and a portion of the second p-type region;
wherein the drain electrode is coupled to the drain of the N-LDMOS transistor, the N-LDMOS transistor being coupled to receive a signal that controls the N-gate of the N-P-LDMOS device and the source of the N-LDMOS transistor being coupled to one of a lower rail and a negative voltage.

16. The N-P-LDMOS device and control circuit as recited in claim 15 wherein the drain electrode is coupled to the drain of the N-LDMOS transistor via a resistor.

17. The N-P-LDMOS device and control circuit as recited in claim 16 wherein the drain electrode is further coupled to the drain of the N-LDMOS transistor via a diode.

18. The N-P-LDMOS device and control circuit as recited in claim 15 wherein the drain electrode is coupled to a source and a gate of a depletion mode PMOS transistor, the depletion-mode PMOS transistor having a drain coupled to the drain of the N-LDMOS transistor.

Assignees

• Texas Instruments Inc

Inventors

• Zhang Yongxi
• Pendharkar Sameer P
• Hower Philip L
• Giombanco Salvatore
• Marino Filippo
• Sridhar Seetharaman

Classifications

• H03K19/018521 Primary

  of complementary type, e.g. CMOS · CPC title

• H03K17/122

  in field-effect transistor switches · CPC title

• H01L27/0928

  Electricity · mapped topic

• H01L27/0922

  Electricity · mapped topic

• H01L29/0634

  Electricity · mapped topic