Analog and audio mixed-signal front end for 4G/LTE cellular system-on-chip

Patent metadata

Field	Value
Publication number	US-9413375-B2
Application number	US-201414586866-A
Country	US
Kind code	B2
Filing date	Dec 30, 2014
Priority date	Jan 3, 2014
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

A CMOS analog and audio front-end circuit includes an enhanced analog-to-digital converter (ADC) that achieves a desired signal-to-noise-and-distortion (SNDR) and an analog-front-end transmit (TX) digital-to-analog converter (DAC). The enhanced ADC includes an improved single Op-Amp resonator coupled to a feed-forward loop and can substantially reduce signal transfer function (STF) peaking of the enhanced ADC. The CMOS analog and audio front-end circuit is integrated with a baseband processor.

First claim

What is claimed is:

1. A CMOS analog and audio front-end circuit, the circuit comprising:
an enhanced analog-to-digital converter (ADC) configured to achieve a desired signal-to-noise-and-distortion (SNDR); and
an analog-front-end transmit (TX) digital-to-analog converter (DAC),
wherein:
the enhanced ADC includes an improved single Op-Amp resonator coupled to a feed-forward loop, the feed-forward loop being coupled between an input node of the enhanced ADC and a node of a twin-T structure of the improved single Op-Amp resonator, and
the CMOS analog and audio front-end circuit is integrated with a baseband processor.

2. The circuit of claim 1 , wherein:
the enhanced ADC comprises a sigma-delta ADC,
the sigma-delta ADC comprises a programmable wideband sigma-delta ADC,
the desired SNDR comprises more than 70 SNR at 9 MHz,
the desired SNDR is scalable with power consumption, and
a lower SNDR corresponds to a lower power consumption.

3. The circuit of claim 2 , wherein:
the enhanced ADC is configured to provide a reduced STF peaking of less than 1 dB,
the programmable wideband sigma-delta ADC comprises a continuous-time (CT) sigma-delta ADC,
the enhanced ADC further comprises a DAC feedback configured to couple a delayed output signal of the enhanced ADC to a first internal node of the single Op-Amp resonator, wherein the DAC feedback is configured to reduce the STF peaking of the enhanced ADC to approximately 5 dB.

4. The circuit of claim 1 , wherein the feed-forward loop comprises a resistor and an inverter, and wherein the feed-forward loop is configured to further reduce the STF peaking, and wherein the improved single Op-Amp resonator is configured to substantially reduce signal transfer function (STF) peaking of the enhanced ADC.

5. The circuit of claim 1 , wherein the enhanced ADC comprises a direct feedback loop that is configured to feed an output signal of the enhanced ADC through a gain stage back to an input of a flash ADC of the enhanced ADC to compensate an excessive loop delay.

6. The circuit of claim 1 , wherein the single Op-Amp resonator comprises a bi-quad resonator implemented with a single Op-Amp and is configured to reduce power consumption and loop filter delay.

7. The circuit of claim 1 , wherein the analog-front-end TX DAC is configured to provide more than 13-bit linearity and less than 8 nV/sqrtHz noise density at 30 MHz.

8. The circuit of claim 1 , wherein:
the analog-front-end TX DAC comprises a push-pull DAC configured by using only one type of transistor,
the push-pull DAC is configured by using only PMOS transistors, and
the push-pull DAC is configured to substantially reduce a drive current, noise, and code-dependent output impedance variation.

9. The circuit of claim 1 , wherein:
the circuit further comprises a high-fidelity audio sub-system configured to provide substantially high linearity,
the high-fidelity audio sub-system is configured to integrate a headset DAC and a power amplifier into the base-band processor without using a buffer circuit between the headset DAC and the power amplifier,
the high-fidelity audio sub-system is configured to provide more than 110 dB SNR in a play-back path and more than 92 dB SNR in a capture path,
the high-fidelity audio sub-system comprises compound complementary switches implemented in laterally-diffused MOS (LDMOS) and configured to close one of a microphone bias path or a data path reliably and level shifters configured to improve total harmonic distortion (THD) for mid-range input voltages.

10. A method of providing a CMOS analog and audio front-end circuit, the method comprising:
providing an enhanced analog-to-digital converter (ADC) configured to achieve a desired signal-to-noise-and-distortion ratio (SNDR);
coupling an improved single Op-Amp resonator of the enhanced ADC to a feed-forward loop coupled between an input node of the enhanced ADC and a node of a twin-T structure of the improved single Op-Amp resonator; and
providing an analog-front-end transmit (TX) digital-to-analog converter (DAC) and configuring the analog-front-end TX DAC to provide a substantial linearity,
wherein,
the enhanced ADC and the analog-front-end TX DAC are integrated with a baseband processor.

11. The method of claim 10 , wherein:
providing the enhanced ADC comprises providing a sigma-delta ADC,
providing the sigma-delta ADC comprises providing a programmable wideband sigma-delta ADC,
achieving the desired SNDR comprises achieving more than 70 SNR at 9 MHz,
the desired SNDR is scalable with power consumption, and
a lower SNDR corresponds to a lower power consumption.

12. The method of claim 11 , further comprising:
configuring the enhanced ADC to provide a reduced STF peaking of less than 1 dB,
providing the programmable wideband sigma-delta ADC comprises providing a continuous-time (CT) sigma-delta ADC,
configuring a DAC feedback of the enhanced ADC to couple a delayed output signal of the enhanced ADC to a first internal node of the single Op-Amp resonator, and
configuring the DAC feedback to reduce the STF peaking of the enhanced ADC to approximately 5 dB.

13. The method of claim 10 , further comprising:
configuring the improved single Op-Amp resonator to substantially reduce signal transfer function (STF) peaking of the enhanced ADC;
configuring the feed-forward loop by using a resistor and an inverter, and
configuring the feed-forward loop to further reduce the STF peaking.

14. The method of claim 10 , further comprising coupling a direct feedback loop to feed an output signal of the enhanced ADC through a gain stage back to an input of a flash ADC of the enhanced ADC to compensate an excessive loop delay.

15. The method of claim 10 , wherein the single Op-Amp resonator comprises a bi-quad resonator implemented with a single Op-Amp, and wherein the method comprises configuring the bi-quad resonator to reduce power consumption and loop filter delay.

16. The method of claim 10 , further comprising configuring the analog-front-end TX DAC to provide more than 13-bit linearity and less than 8 nV/sqrtHz noise density at 30 MHz.

17. The method of claim 10 , further comprising:
configuring a push-pull DAC of the analog-front-end TX DAC by using only one type of transistor,
configuring the push-pull DAC by using only PMOS transistors, and
configuring the push-pull DAC to substantially reduce a drive current, noise, and a code-dependent output impedance variation.

18. The method of claim 10 , further comprising:
providing a high-fidelity audio sub-system integrated with the baseband processor,
configuring the high-fidelity audio sub-system to integrate a headset DAC and a power amplifier into the base-band processor without using a buffer circuit between the headset DAC and the power amplifier,
configuring the high-fidelity audio sub-system to provide more than 110 dB SNR in a play-back path and more than 92 dB SNR in a capture path,
implementing compound complementary switches of the high-fidelity audio sub-system in laterally-diffused MOS (LDMOS), and
configuring the compound complementary switches to close one of a microphone bias path or a data path reliably and level shifters configured to improve total harmonic distortion (THD) for mid-range input voltages.

19. A communication device, comprising:
a radio-frequency integrated circuit (RFIC) configured to communicate RF signals; and
a baseband processor coupled to the RFIC, the baseband processor including a CMOS analog and audio front-end circuit comprising:

Assignees

• Broadcom Corp

Inventors

• Jiang Xicheng
• Yu Xinyu
• Lin Fang
• Cheung Yee Ling
• Inerfield Michael

Classifications

• H04M1/0202

  Portable telephone sets, e.g. cordless phones, mobile phones or bar type handsets (constructional features of telephone transmitters or receivers, e.g. of speakers or microphones H04M1/03) · CPC title

• H04B1/1646

  adapted for the reception of stereophonic signals · CPC title

• H04B1/40

  Circuits · CPC title

• H03M1/185 Primary

  the determination of the range being based on more than one digital output value, e.g. on a running average, a power estimation or the rate of change · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title