Method of forming internal dielectric spacers for horizontal nanosheet FET architectures

Patent metadata

Field	Value
Publication number	US-9905672-B2
Application number	US-201615276784-A
Country	US
Kind code	B2
Filing date	Sep 26, 2016
Priority date	May 23, 2016
Publication date	Feb 27, 2018
Grant date	Feb 27, 2018

Abstract

A method to form a nanosheet stack for a semiconductor device includes forming a stack of a plurality of sacrificial layers and at least one channel layer on an underlayer in which a sacrificial layer is in contact with the underlayer, each channel layer being in contact with at least one sacrificial layer, the sacrificial layers are formed from SiGe and the at least one channel layer is formed from Si; forming at least one source/drain trench region in the stack to expose surfaces of the SiGe sacrificial layers and a surface of the at least one Si channel layer; and oxidizing the exposed surfaces of the SiGe sacrificial layers and the exposed surface of the at least one Si layer in an environment of wet oxygen, or ozone and UV.

First claim

What is claimed is:

1. A method to form a nanosheet stack for a semiconductor device, the method comprising:
forming a stack of a plurality of sacrificial layers and at least one channel layer on an underlayer,
each channel layer being in contact with at least one sacrificial layer, and
the sacrificial layers being formed of SiGe and the at least one channel layer being formed of Si;
forming at least one source/drain trench region in the stack to expose first surfaces of the SiGe sacrificial layers and a first surface of the at least one Si channel layer;
oxidizing the exposed first surfaces of the SiGe sacrificial layers to form oxidized SiGe sacrificial layers and the exposed first surface of the at least one Si layer to form an oxidized Si channel layer in an environment of wet oxygen, or ozone and UV,
wherein the oxidized SiGe sacrificial layers include outer parts overlapped with the oxidized Si channel layer and inner parts non-overlapped with the oxidized Si channel layer;
removing the oxidized Si channel layer to expose a second surface of the at least one Si layer; and
removing partially the oxidized SiGe sacrificial layers so that the outer parts of the oxidized SiGe sacrificial layers are removed and the inner parts of the oxidized SiGe sacrificial layers remain,
wherein the removing of the oxidize Si channel layer and the removing partially of the oxidized SiGe sacrificial layers are performed at substantially the same time.

2. The method of claim 1 ,
wherein the SiGe sacrificial layers comprise a percentage of Ge that is at least about 25% to about 75% Ge.

3. The method of claim 1 ,
wherein the at least one Si channel layer comprises a tensile stress.

4. The method of claim 1 ,
wherein a length of the oxidized SiGe sacrificial layers is at least four times greater than a length of the oxidized Si channel layer.

5. The method of claim 4 ,
wherein the length of the oxidized SiGe sacrificial layers is at least 20 times greater than the length of the oxidized Si channel layer.

6. The method of claim 1 ,
wherein the oxidized SiGe layers are seamless.

7. A method to form an internal spacer in a nanosheet stack, the method comprising:
forming an underlayer;
forming alternately a plurality of sacrificial layers and a plurality of channel layers on the underlayer to form a stack of the plurality of sacrificial layers and the plurality of channel layers,
a bottommost sacrificial layer of the plurality of sacrificial layers being in direct contact with the underlayer, and
the plurality of sacrificial layers being formed of SiGe and the plurality of channel layers being formed of Si;
forming a first source/drain trench region and a second source/drain trench region in the stack to expose surfaces of the SiGe sacrificial layers and surfaces of the Si channel layers in each of the first source/drain trench region and the second source/drain trench region;
oxidizing the exposed surfaces of the SiGe sacrificial layers and the exposed surfaces of the Si channel layers to form oxidized SiGe sacrificial layers and oxidized Si channel layers at a temperature between about 400° C. and about 800° C. in an environment of wet oxygen, or ozone and UV,
a length of the oxidized SiGe sacrificial layers between the first and second source/drain trench regions being at least four times greater than a length of the oxidized Si channel layers between the first and second source/drain trench regions,
the oxidized SiGe sacrificial layers including outer parts overlapped with the oxidized Si channel layers and inner parts non-overlapped with the oxidized Si channel layers; and
removing partially the oxidized SiGe sacrificial layers so that the outer parts of the oxidized SiGe sacrificial layers are removed and the inner parts of the oxidized SiGe sacrificial layers remain.

8. The method of claim 7 ,
wherein the SiGe sacrificial layers comprise a percentage of Ge that is at least about 25% Ge.

9. The method of claim 8 ,
wherein the SiGe sacrificial layers comprise a percentage of Ge that is greater than about 25% Ge.

10. The method of claim 7 ,
wherein the Si channel layers comprises a tensile stress.

11. The method of claim 10 ,
wherein the Si channel layers comprise an nFET device.

12. The method of claim 7 ,
wherein a distance through the stack between the first and second source/drain trench regions is less than about 200 nm.

13. The method of claim 12 ,
wherein the length of the oxidized SiGe sacrificial layers between the first and second source/drain trench regions is at least 20 times greater than the length of the oxidized Si channel layers between the first and second source/drain trench regions.

14. The method of claim 7 ,
wherein the underlayer has a surface orientation of (100), (110) or (111).

15. A method to form a stack for a semiconductor device, the method comprising:
forming alternately a plurality of SiGe sacrificial layers and a plurality of Si channel layers on an underlayer to form a stack of the plurality of SiGe sacrificial layers and the plurality of Si channel layers;
forming a plurality of source/drain trench regions in the stack to expose surfaces of the SiGe sacrificial layers and surfaces the Si channel layers; and
oxidizing the exposed surfaces of the SiGe sacrificial layers to form oxidized SiGe sacrificial layers and the exposed surfaces of the Si channel layers to form oxidized Si layers in an environment of wet oxygen, or ozone and UV,
wherein the oxidized SiGe sacrificial layers include outer parts overlapped with the oxidized Si channel layers and inner parts non-overlapped with the oxidized Si channel layers;
removing the oxidized Si channel layers; and
removing partially the oxidized SiGe sacrificial layers so that the outer parts of the oxidized SiGe sacrificial layers are removed and each of the inner parts of the oxidized SiGe sacrificial layers is interposed between two adjacent Si channel layers that remain unoxidized after the oxidizing of the exposed surfaces of the Si channel layers.

16. The method of claim 15 ,
wherein the plurality of Si channel layers comprise a tensile stress.

17. The method of claim 15 ,
wherein a length of the oxidized SiGe sacrificial layers is at least four times greater than a length of the oxidized Si channel layers.

18. The method of claim 17 ,
wherein the length of the oxidized SiGe sacrificial layers is at least 20 times greater than the length of the oxidized Si channel layers.

19. The method of claim 1 ,
wherein the oxidized Si channel layer removed and the outer parts of the oxidized SiGe sacrificial layers partially removed have substantially the same thickness.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Wang Wei E
• Rodder Mark S
• Obradovic Borna J
• Palle Dharmendar Reddy
• Hong Joon Goo

Classifications

• H10P14/6308

  of Group IV semiconductors · CPC title

• H10P14/3452

  Microstructure · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/3211

  Silicon, silicon germanium or germanium · CPC title

• H01L29/66636

  Electricity · mapped topic