Semiconductor device

Patent metadata

Field	Value
Publication number	US-9972701-B2
Application number	US-201715443160-A
Country	US
Kind code	B2
Filing date	Feb 27, 2017
Priority date	Feb 29, 2016
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

A semiconductor device includes a fin-type active area, nanosheets, a gate, a source/drain region, and insulating spacers. The fin-type active area protrudes from a substrate in a first direction. The nanosheets are spaced from an upper surface of the fin-type active area and include channel regions. The gate is over the fin-type active area. The source/drain region is connected to the nanosheets. The insulating spacers are in the fin-type active area and between the nanosheets. Air spaces are between the insulating spacers and the source/drain region based on positions of the insulating spacers.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a fin-type active area protruding from a substrate in a first direction;
a plurality of nanosheets spaced from and extending parallel to an upper surface of the fin-type active area, each of the nanosheets including a channel region;
a gate extending over the fin-type active area in a second direction crossing the first direction and surrounding at least some of the nanosheets;
a source/drain region connected to the nanosheets; and
insulating spacers disposed between the upper surface of the fin-type active area and the nanosheets, disposed between the nanosheets, wherein air spaces are between the insulating spacers and the source/drain region based on positions of the insulating spacers.

2. The semiconductor device as claimed in claim 1 , wherein:
the gate includes a first gate portion with a first thickness on the nanosheets and a plurality of second gate portions filling spaces between the fin-type active area and the nanosheets, each of the second gate portions having a second thickness less than the first thickness, and
the insulating spacers cover side walls of the second gate portions.

3. The semiconductor device as claimed in claim 2 , wherein the second gate portions are longer than the first gate portion in the first direction.

4. The semiconductor device as claimed in claim 3 , wherein a lowermost one of the second gate portions is thicker than other ones of the second gate portions.

5. The semiconductor device as claimed in claim 2 , wherein a volume of air spaces between insulating spacers covering side walls of a lowermost one of the second gate portions and the source/drain region is different from volumes of air spaces between insulating spacers covering side walls of other ones of the second gate portions and the source/drain region.

6. The semiconductor device as claimed in claim 5 , wherein vertical heights of the insulating spacers covering the side walls of the lowermost one of the second gate portion is different from heights of the insulating spacers covering the side walls of the other ones of the second gate portions.

7. The semiconductor device as claimed in claim 1 , wherein a vertical height of the insulating spacers covering the side walls of the lowermost one of the second gate portions is less than those of the insulating spacers covering the side walls of other ones of the second gate portions.

8. The semiconductor device as claimed in claim 1 , wherein vertical heights of the air spaces with respect to the upper surface of the fin-type active area decrease in a direction toward the source/drain region.

9. The semiconductor device as claimed in claim 1 , wherein the air space extends between the nanosheets and the fin-type active area.

10. The semiconductor device as claimed in claim 1 , wherein each of the air spaces protrudes toward the insulating spacer.

11. A semiconductor device, comprising:
a substrate including an active area;
at least one nanosheet stack structure spaced from and facing an upper surface of the active area, the at least one nanosheet stack structure including a plurality of nanosheets, each of the nanosheets including a channel region;
a gate extending over the active area in a second direction and covering the at least one nanosheet stack structure, the gate including a first gate portion on the at least one nanosheet stack structure and a plurality of second gate portions, each of the plurality of second gate portions being under a lower side of each of the nanosheets;
a gate dielectric layer between the at least one nanosheet stack structure and the gate;
a source/drain region connected to one end of each of neighboring ones of the nanosheets;
a first insulating spacer on the nanosheets and covering side walls of the gate; and
a plurality of second insulating spacers disposed between the gate and the source/drain region, disposed between the upper surface of the active area and the at least one nanosheet stack structure, and disposed between the nanosheets, wherein a plurality of air spaces are disposed between the plurality of second insulating spacers and a first area of the source/drain region based on positions of the plurality of second insulating spacers and disposed to overlap a second area of the source/drain region.

12. The semiconductor device as claimed in claim 11 , wherein: a volume of at least one of the air spaces at a first level with respect to the upper surface of the active area is different from volumes of air spaces at one or more different levels.

13. The semiconductor device as claimed in claim 11 , wherein each of the second gate portions is longer than the first gate portion.

14. The semiconductor device as claimed in claim 11 , wherein vertical heights of the air spaces with respect to the upper surface of the active area decrease in a direction from the plurality of second insulating spacers to the source/drain region.

15. A semiconductor device, comprising:
a substrate including an active area;
at least one nanosheet stack structure spaced from and facing an upper surface of the active area, the at least one nanosheet stack structure including a plurality of nanosheets, each of the nanosheets including a channel region;
a gate extending over the active area in a second direction and covering the at least one nanosheet stack structure, the gate including a first gate portion on the at least one nanosheet stack structure and a plurality of second gate portions on a lower side of each of the nanosheets;
a source/drain region connected to one end of each of neighboring ones of the nanosheets; and
a plurality of first insulating spacers between the gate and the source/drain region in spaces between the upper surface of the active area and the at least one nanosheet stack structure and spaces between the nanosheets, wherein a plurality of air spaces are between the plurality of first insulating spacers and a first area of the source/drain region and overlapping a second area of the source/drain region.

16. The semiconductor device as claimed in claim 15 , wherein each of the plurality of air spaces is disposed on a side surface of each of the plurality of first insulating spacers, and each of the plurality of air spaces tapers in width in a direction toward the source/drain region.

17. The semiconductor device as claimed in claim 15 , wherein each of the plurality of air spaces protrudes toward the first insulating spacer.

18. The semiconductor device as claimed in claim 15 , wherein a volume of at least one of the air spaces at a first level with respect to the upper surface of the active area is different from volumes of air spaces at one or more different levels.

19. The semiconductor device as claimed in claim 15 , wherein each of the plurality of second gate portions is longer than the first gate portion.

20. The semiconductor device as claimed in claim 15 , wherein vertical heights of the air spaces with respect to the upper surface of the active area decrease in a direction from the first insulating spacers to the source/drain region.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Dong-Woo
• Lee Hyun-Jung
• Kim Sun-Jung
• Lee Seung-Hun
• Park Keum-Seok
• Cho Edward Namkyu

Classifications

• H01L29/1037

  Electricity · mapped topic

• H01L29/515

  Electricity · mapped topic

• H01L29/66439

  Electricity · mapped topic

• H01L29/0673

  Electricity · mapped topic

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title