Method for direct bonding of III-V semiconductor substrates with a radical oxide layer

Patent metadata

Field	Value
Publication number	US-10586783-B2
Application number	US-201615340377-A
Country	US
Kind code	B2
Filing date	Nov 1, 2016
Priority date	Nov 9, 2015
Publication date	Mar 10, 2020
Grant date	Mar 10, 2020

Abstract

A manufacturing method including supplying a first substrate including a first face designated front face, the front face being made of a III-V type semiconductor, supplying a second substrate, forming a radical oxide layer on the front face of the first substrate by executing a radical oxidation, assembling, by a step of direct bonding, the first substrate and the second substrate so as to form an assembly including the radical oxide layer intercalated between the first and second substrates, executing a heat treatment intended to reinforce the assembly interface, and making disappear, at least partially, the radical oxide layer.

First claim

The invention claimed is:

1. A manufacturing method, comprising:
forming a first radical oxide layer on a first front face of a first substrate by executing a radical oxidation,
assembling, by a direct bonding, the first substrate and a second substrate so as to form an assembly having an assembly interface comprising the first radical oxide layer intercalated between the first and second substrates, and
executing a heat treatment for reinforcing the assembly interface so that the first radical oxide layer disappears, at least partially, and the assembly interface becomes electrically conducting,
wherein
the first front face is made of a III-V type semiconductor, and
the radical oxidation is executed under an atmosphere of ozone and/or of oxygen illuminated by ultraviolet radiation.

2. The manufacturing method according to claim 1 , wherein the radical oxidation is executed at atmospheric pressure.

3. The manufacturing method according to claim 1 , further comprising:
de-oxidizing the first front face before forming the first radical oxide layer.

4. The manufacturing method according to claim 1 , wherein the direct bonding is executed under a controlled humidity atmosphere according to one of the following conditions:
under an atmosphere having a water partial pressure of less than 10 −1 Pa, and
under a partial vacuum having a pressure of less than 10 Pa.

5. The manufacturing method according to claim 1 , wherein the first radical oxide layer has a thickness of less than 5 nm.

6. The manufacturing method according to claim 1 , wherein the ultraviolet radiation is executed with a first primary illumination wavelength λ 1 satisfying expression (1) and a second primary illumination wavelength λ 2 satisfying expression (2):
λ 1 <240 nm  (1),

240 nm<λ 2 <320 nm  (2).

7. The manufacturing method according to claim 6 , wherein λ 1 is 184.9 nm.

8. The manufacturing method according to claim 6 , wherein λ 2 is 253.7 nm.

9. The manufacturing method according to claim 1 , wherein the second substrate comprises at least one element selected from the group consisting of silicon, germanium, an alloy of silicon/germanium, sapphire, alumina, glass, quartz, and SiC.

10. The manufacturing method according to claim 1 , wherein
the second substrate comprises a second front face made of a III-V type semiconductor,
the method further comprises: forming a second radical oxide layer by the radical oxidation on the second front face, and
the second radical oxide layer contacts the first radical oxide layer after the direct bonding.

11. The manufacturing method according to claim 10 , further comprising:
de-oxidizing the second front face before forming the second radical oxide layer.

12. The manufacturing method according to claim 10 , wherein the second substrate comprises at least one element selected from the group consisting of InP, GaAs, In 1-x As x P, InP 1-y Ga y , In 1-x As x P 1-y Ga y , and an alloy of Group III and Group V materials.

13. The manufacturing method according to claim 10 , wherein the second radical oxide layer has a thickness of less than 5 nm.

14. The manufacturing method according to claim 10 , wherein the second radical oxide layer has a thickness of less than 3 nm.

15. The manufacturing method according claim 1 , wherein the first substrate comprises at least one element selected from the group consisting of InP, GaAs, In 1-x As x P, InP 1-y Ga y , In 1-x As x P 1-y Ga y , and an alloy of Group III and Group V materials.

16. The manufacturing method according to claim 1 , wherein the first radical oxide layer has a thickness of less than 3 nm.

17. The manufacturing method according to claim 1 , wherein the heat treatment is executed at a temperature of from 200° C. to less than 600° C.

18. The manufacturing method according to claim 1 , wherein the radiation oxidation is executed at a temperature of less than 400° C.

19. The manufacturing method according to claim 1 , wherein the first front face contains hydrocarbons, which are transformed into volatile species by the radical oxidation during said forming.

Assignees

• Commissariat Energie Atomique
• Soitec Silicon On Insulator

Inventors

• Moriceau Hubert
• Imbert Bruno
• Blot Xavier

Classifications

• H01L21/187

  Electricity · mapped topic

• H01L24/83 Primary

  Electricity · mapped topic

• H01L21/76251

  Electricity · mapped topic

• H01L33/0079

  Electricity · mapped topic

• H01L2224/83935

  Electricity · mapped topic