Fan-out semiconductor package

Patent metadata

Field	Value
Publication number	US-10580759-B2
Application number	US-201816152237-A
Country	US
Kind code	B2
Filing date	Oct 4, 2018
Priority date	Feb 26, 2018
Publication date	Mar 3, 2020
Grant date	Mar 3, 2020

Abstract

A fan-out semiconductor package includes a first core member including a first through-hole, a first semiconductor chip disposed in the first through-hole of the first core member, a first encapsulant configured to encapsulate at least a portion of the first semiconductor chip, a first connection member disposed on the first semiconductor chip and including a first redistribution layer, a second core member adhered to a lower surface of the first connection member and including a second through-hole, a second semiconductor chip disposed in the second through-hole of the second core member, a second encapsulant configured to encapsulate the second semiconductor chip, the second core member, and the first connection member, a second connection member disposed on the second semiconductor chip and including a second redistribution layer, and a connection via penetrating through the second core member and configured to electrically connect the first redistribution layer and the second redistribution layer.

First claim

What is claimed is:

1. A fan-out semiconductor package comprising:
a first core member including a first through-hole;
a first semiconductor chip disposed in the first through-hole of the first core member and including a first active surface with a first connection pad disposed thereon and a first non-active surface opposing the first active surface;
a first encapsulant configured to encapsulate at least a portion of the first semiconductor chip;
a first connection member disposed on the first active surface of the first semiconductor chip and including a first via and a first redistribution layer electrically connected to the first connection pad through the first via;
a second core member adhered to a lower surface of the first connection member and including a second through-hole;
a second semiconductor chip disposed in the second through-hole of the second core member and including a second active surface with a second connection pad disposed thereon and a second non-active surface opposing the second active surface;
a second encapsulant configured to encapsulate the second semiconductor chip, the second core member, and the first connection member;
a second connection member disposed on the second active surface of the second semiconductor chip and including a second via and a second redistribution layer, electrically connected to the second connection pad through the second via; and
a connection via penetrating through the second core member and configured to electrically connect the first redistribution layer and the second redistribution layer,
wherein the first encapsulant covers the first non-active surface of the first semiconductor chip and the second encapsulant covers a portion of the second active surface of the second semiconductor chip.

2. The fan-out semiconductor package of claim 1 , wherein the second core member further includes a via through-hole with the connection via disposed therein; and
wherein the connection via penetrates through the second encapsulant in the via through-hole.

3. The fan-out semiconductor package of claim 1 , wherein the second core member and the second non-active surface of the second semiconductor chip are adhered to the first connection member using a die attach film (DAF) as a medium.

4. The fan-out semiconductor package of claim 1 , wherein the connection via has a greater diameter than the first and second vias.

5. The fan-out semiconductor package of claim 1 , wherein the connection via has a tapered shape with a lower diameter greater than an upper diameter.

6. The fan-out semiconductor package of claim 1 , wherein the first connection pad connected to the first via is redistributed externally of the first semiconductor chip through the first redistribution layer; and
wherein the second connection pad connected to the second via is redistributed externally of the second semiconductor chip through the second redistribution layer.

7. The fan-out semiconductor package of claim 1 , wherein the first core member includes a first core insulating layer, a first wiring layer contacting the first connection member and embedded in the first core insulating layer, and a second wiring layer disposed at an opposite side of the first core insulating layer to a side in which the first wiring layer is embedded; and
wherein the first and second wiring layers are electrically connected to the first connection pad.

8. The fan-out semiconductor package of claim 1 , wherein the first core member includes a first core insulating layer, and a first wiring layer and a second wiring layer that are arranged on opposite surfaces of the first core insulating layer, respectively; and
wherein the first and second wiring layers are electrically connected to the first connection pad.

9. A fan-out semiconductor package comprising:
a first core member including a first through-hole;
a first semiconductor chip disposed in the first through-hole of the first core member and including a first active surface with a first connection pad disposed therein and a first non-active surface opposing the first active surface;
a first encapsulant configured to encapsulate at least a portion of the first semiconductor chip;
a first connection member disposed on the first active surface of the first semiconductor chip and including a first via and a first redistribution layer electrically connected to the first connection pad through the first via;
a second semiconductor chip disposed below the first connection member and including a second active surface with a second connection pad disposed thereon and a second non-active surface opposing the second active surface;
a second encapsulant configured to encapsulate the second semiconductor chip and the first connection member;
a second connection member disposed on the second active surface of the second semiconductor chip and including a second via and a second redistribution layer, electrically connected to the second connection pad through the second via;
a first connection via penetrating through the second encapsulant and electrically connecting the first redistribution layer and the second redistribution layer;
a second core member disposed below the second connection member and including a second through-hole;
a third semiconductor chip disposed in the second through-hole of the second core member and including a third active surface with a third connection pad disposed thereon and a third non-active surface opposing the third active surface;
a third encapsulant configured to encapsulate the third semiconductor chip, the second core member, and the second connection member;
a third connection member disposed on the third active surface of the third semiconductor chip and including a third via and a third redistribution layer electrically connected to the third connection pad through the third via; and
a second connection via penetrating through the second core member and electrically connecting the second redistribution layer and the third redistribution layer.

10. The fan-out semiconductor package of claim 9 , wherein the first and second core members are formed of a different material from the second encapsulant.

11. The fan-out semiconductor package of claim 10 , wherein the first and second core members are formed of the same material.

12. The fan-out semiconductor package of claim 9 , wherein the first encapsulant covers the first non-active surface of the first semiconductor chip, the second encapsulant covers the second active surface of the second semiconductor chip, and the third encapsulant covers the third active surface of the third semiconductor chip.

13. The fan-out semiconductor package of claim 9 , wherein the first and second connection vias are arranged below the first core member in an external region of the second and third semiconductor chips, respectively.

14. The fan-out semiconductor package of claim 13 , wherein the first and second connection vias are arranged at different positions on a plane.

15. The fan-out semiconductor package of claim 13 , wherein the first and second connection vias are stacked in one line in a stack direction of the first to third semiconductor chips.

16. A fan-out semiconductor package, comprising:
a first connection member comprising a first insulating layer, a first redistribution layer disposed on the first insulating layer, a second insulating layer disposed on the first redistribution layer, and a first via connected to the first redistribution layer and penetrating through the first insulating layer;
a first semiconductor chip having a first active

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jo Eun Jung
• Kim Han
• Seo Yoon Seok

Classifications

• H01L2224/08235

  Electricity · mapped topic

• H01L2224/32225

  Electricity · mapped topic

• H01L24/32

  Electricity · mapped topic

• H01L23/3128

  Electricity · mapped topic

• H01L24/08

  Electricity · mapped topic