Methods of gate replacement in semiconductor devices

Patent metadata

Field	Value
Publication number	US-10128237-B2
Application number	US-201615191598-A
Country	US
Kind code	B2
Filing date	Jun 24, 2016
Priority date	Jun 24, 2016
Publication date	Nov 13, 2018
Grant date	Nov 13, 2018

Abstract

A method of forming a semiconductor device includes forming a plurality of fins on a substrate, forming a polysilicon gate structure, and replacing the polysilicon gate structure with a metal gate structure. Replacing the polysilicon gate structure includes depositing a work function metal layer over the plurality of fins, forming a metal oxide layer over the work function metal layer, and depositing a first metal layer over the metal oxide layer. A first portion of the metal oxide layer is formed within an area between adjacent fins from among the plurality of fins. An example benefit includes reduced diffusion of unwanted and/or detrimental elements from the first metal layer into its underlying layers and consequently, the reduction of the negative impact of these unwanted and/or detrimental elements on the semiconductor device performance.

First claim

What is claimed is:

1. A method of forming a semiconductor device, the method comprising:
forming a plurality of fins on a substrate;
forming a polysilicon gate structure on the plurality of fins; and
replacing the polysilicon gate structure with a metal gate structure, wherein the replacing comprises:
depositing a work function metal layer over the plurality of fins;
depositing a first metal layer over the work function metal layer;
forming a metal oxide layer over the first metal layer, wherein a portion of the metal oxide layer fills an area between adjacent fins of the plurality of fins; and
depositing a second metal layer on the metal oxide layer, wherein the metal oxide layer prevents a diffusion of elements from the second metal layer into the work function metal layer.

2. The method of claim 1 , wherein the forming the metal oxide layer comprises oxidizing the first metal layer.

3. The method of claim 1 , wherein the forming the metal oxide layer comprises
oxidizing the first metal layer in air, oxygen plasma, water, nitric oxide, or a combination thereof.

4. The method of claim 1 , wherein the portion of the metal oxide layer comprises voids or air pockets.

5. The method of claim 1 , wherein another portion of the metal oxide layer is formed over the plurality of fins.

6. The method of claim 1 , wherein an interface between the metal oxide layer and the second metal layer is formed below or coplanar with a top surface of at least one fin of the plurality of fins.

7. The method of claim 1 , further comprising forming an interlayer dielectric layer (ILD) over the plurality of fins.

8. The method of claim 7 , wherein the replacing the polysilicon gate structure further comprises planarizing the second metal layer, the metal oxide layer, the first metal layer, and the work function metal layer to be coplanar with a top surface of the ILD layer.

9. The method of claim 1 , wherein the second metal layer comprises tungsten, aluminum, or cobalt.

10. The method of claim 1 , wherein the first metal layer comprises tungsten (W), aluminum (Al), cobalt (Co), titanium (Ti), silver (Ag), manganese (Mn), zirconium (Zr), copper (Cu), nickel (Ni), or a combination thereof.

11. A method, comprising:
forming a plurality of fins on a substrate;
forming a polysilicon structure on the plurality of fins; and
replacing the polysilicon structure with a gate structure, wherein the replacing comprising:
depositing a work function metal layer over the plurality of fins;
depositing a first metal layer over the work function metal layer;
forming a passivation layer over the first metal layer, wherein a portion of the passivation layer fills an area between adjacent fins of the plurality of fins; and
depositing a second metal layer on the passivation layer, wherein the passivation layer prevents a diffusion of elements from the second metal layer into the work function metal layer.

12. The method of claim 11 , wherein the portion of the passivation layer comprises voids or air pockets.

13. The method of claim 11 , wherein the passivation layer comprises a metal oxide.

14. The method of claim 11 , wherein the forming the passivation layer comprises
oxidizing the first metal layer in air, oxygen plasma, water, nitric oxide, or a combination thereof.

15. The method of claim 11 , wherein the passivation layer comprises a metal oxide of tungsten (W), aluminum (Al), cobalt (Co), titanium (Ti), silver (Ag), manganese (Mn), zirconium (Zr), copper (Cu), nickel (Ni), or a combination thereof.

16. A method of forming a semiconductor device, the method comprising:
forming a plurality of fins on a substrate;
depositing a work function metal layer over the plurality of fins;
depositing a first metal layer over the work function metal layer;
forming a diffusion barrier layer over the first metal layer, a portion of the diffusion barrier layer being formed within an area between adjacent fins of the plurality of fins; and
depositing a second metal layer on the diffusion barrier layer, wherein the diffusion barrier layer prevents a diffusion of elements from the second metal layer into the work function metal layer.

17. The method of claim 16 , wherein the forming the diffusion barrier layer comprises oxidizing the first metal layer.

18. The method of claim 16 , wherein the forming the diffusion barrier layer comprises
oxidizing the first metal layer in air, oxygen plasma water, nitric oxide, or a combination thereof.

19. The method of claim 16 , wherein the portion of the diffusion barrier layer comprises voids or air pockets.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsau Hsueh Wen
• Lee Chia-Ching
• WU Chung-Chiang
• Lee Da-Yuan

Classifications

• H10P95/04

  Planarisation of conductive or resistive materials · CPC title

• H10P14/6314

  of a metallic layer · CPC title

• H10D64/01316

  the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al · CPC title

• H10D64/01318 Primary

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H01L21/28088

  Electricity · mapped topic