Lateral bipolar transistor and CMOS hybrid technology

Patent metadata

Field	Value
Publication number	US-9105650-B2
Application number	US-201414186512-A
Country	US
Kind code	B2
Filing date	Feb 21, 2014
Priority date	Sep 12, 2012
Publication date	Aug 11, 2015
Grant date	Aug 11, 2015

Abstract

A method of forming a lateral bipolar transistor includes forming a silicon on insulator (SOI) substrate having a bottom substrate layer, a buried oxide layer (BOX) on top of the substrate layer, and a silicon on insulator (SOI) layer on top of the BOX layer, forming a dummy gate and spacer on top of the silicon on insulator layer, doping the SOI layer with positive or negative ions, depositing an inter layer dielectric (ILD), using chemical mechanical planarization (CMP) to planarize the ILD, removing the dummy gate creating a gate trench which reveals the base of the dummy gate, doping the dummy gate base, depositing a layer of polysilicon on top of the SOI layer and into the gate trench, etching the layer of polysilicon so that it only covers the dummy gate base, and applying a self-aligned silicide process.

First claim

The invention claimed is:

1. A method of forming a lateral bipolar transistor, the method comprising:
forming a silicon on insulator (SOI) substrate having a bottom substrate layer, a buried oxide layer (BOX) on top of the substrate layer, and a silicon on insulator (SOI) layer on top of the BOX layer;
forming a dummy gate and spacer on top of the silicon on insulator layer;
initially doping the SOI layer at opposing sides of the dummy gate and spacer with dopant atoms of a fi…

Assignees

• IBM

Inventors

• Chang Josephine B
• Lauer Gen Pei
• Lauer Isaac
• Sleight Jeffrey W

Classifications

• H10D86/01

  Electricity · mapped topic

• H10D10/311

  Electricity · mapped topic

• H10D10/061

  Electricity · mapped topic

• H10D10/041 Primary

  Electricity · mapped topic

• H01L21/84

  Electricity · mapped topic