Integrated fan-out packages with embedded heat dissipation structure

Patent metadata

Field	Value
Publication number	US-10566261-B2
Application number	US-201815940623-A
Country	US
Kind code	B2
Filing date	Mar 29, 2018
Priority date	Nov 15, 2017
Publication date	Feb 18, 2020
Grant date	Feb 18, 2020

Abstract

A semiconductor structure includes a die embedded in a molding material, the die having die connectors on a first side; a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors; a second redistribution structure at a second side of the die opposing the first side; and a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.

First claim

What is claimed is:

1. A semiconductor structure comprising:
a die embedded in a molding material, the die having die connectors on a first side;
a dummy metal layer contacting and extending along a second side of the die opposing the first side, the dummy metal layer having a same width as the die such that sidewalls of the dummy metal layer are aligned with respective sidewalls of the die;
a first redistribution structure at the first side of the die, the first redistribution structure being electrically coupled to the die through the die connectors;
a second redistribution structure at the second side of the die; and
a thermally conductive material in the second redistribution structure, the die being interposed between the thermally conductive material and the first redistribution structure, the thermally conductive material extending through the second redistribution structure, and the thermally conductive material being electrically isolated.

2. The semiconductor structure of claim 1 , wherein the thermally conductive material comprises an adhesive material with metal particles dispersed therein.

3. The semiconductor structure of claim 1 , further comprising a metal pillar extending through the molding material, the metal pillar electrically coupling the first redistribution structure to the second redistribution structure.

4. The semiconductor structure of claim 1 , wherein the second redistribution structure further comprises dummy metal patterns, wherein the dummy metal patterns contact the thermally conductive material.

5. The semiconductor structure of claim 4 , further comprising a dielectric film between the second redistribution structure and the die, sidewalls of the dielectric film being aligned with respective sidewalls of the die, wherein the thermally conductive material extends from a first side of the dielectric film to an opposing second side of the dielectric film.

6. The semiconductor structure of claim 1 , wherein the thermally conductive material physically contacts the dummy metal layer.

7. The semiconductor structure of claim 6 , wherein the second redistribution structure further comprises dummy metal patterns, wherein the thermally conductive material is disposed between individual ones of the dummy metal patterns.

8. The semiconductor structure of claim 7 , further comprising a dielectric film between the second redistribution structure and the dummy metal layer, the dielectric film having a same width with the dummy metal layer, wherein the thermally conductive material extends through the dielectric film.

9. The semiconductor structure of claim 1 , wherein a surface of the thermally conductive material distal the die is level with a surface of the second redistribution structure distal the die.

10. The semiconductor structure of claim 1 , wherein a surface of the thermally conductive material distal the die is closer to the die than a surface of the second redistribution structure distal the die.

11. The semiconductor structure of claim 1 , wherein a surface of the thermally conductive material distal the die is further from the die than a surface of the second redistribution structure distal the die.

12. A semiconductor structure comprising:
a first redistribution structure;
a second redistribution structure;
a die interposed between the first redistribution structure and the second redistribution structure, wherein a front side of the die faces the first redistribution structure;
a molding material around the die and interposed between the first redistribution structure the second redistribution structure;
a heat dissipation structure at least partially embedded in the second redistribution structure, wherein the heat dissipation structure is electrically isolated and extends from a first side of the second redistribution structure to an opposing second side of the second redistribution structure, and wherein the die is between the heat dissipation structure and the first redistribution structure;
a dielectric film between the second redistribution structure and the die, wherein the dielectric film has a same width as the die, and wherein the heat dissipation structure extends from a first side of the dielectric film to an opposing second side of the dielectric film; and
a semiconductor package electrically coupled to the second redistribution structure.

13. The semiconductor structure of claim 12 , wherein the heat dissipation structure comprises:
dummy metal patterns of the second redistribution structure; and
a metal paste at least partially embedded in the second redistribution structure, the metal paste contacting the dummy metal patterns.

14. The semiconductor structure of claim 12 , wherein a first surface of the heat dissipation structure facing the die is closer to the die than a first side of the second redistribution structure facing the die.

15. A semiconductor structure comprising:
a die attached to a first side of a first redistribution structure;
a conductive pillar on the first side of the first redistribution structure;
a molding material around the die and the conductive pillar;
a second redistribution structure over the die, the conductive pillar and the molding material;
a metal paste embedded in the second redistribution structure and disposed within lateral extents of the die, the metal paste extending through the second redistribution structure, and the metal paste being electrically isolated; and
a dummy metal layer between the die and the metal paste, wherein the dummy metal layer and the die have a same width.

16. The semiconductor structure of claim 15 , further comprising a semiconductor package bonded to conductive features of the second redistribution structure, wherein an upper surface of the metal paste facing the semiconductor package is closer to the semiconductor package than an upper surface of the second redistribution structure facing the semiconductor package.

17. The semiconductor structure of claim 1 , wherein the second redistribution structure has dummy metal patterns and dielectric layers, the dummy metal patterns being separated from the dummy metal layer by at least one of the dielectric layers of the second redistribution structure.

18. The semiconductor structure of claim 1 , wherein thermally conductive material is a metal paste.

19. The semiconductor structure of claim 18 , wherein the thermally conductive material and the dummy metal layer have different compositions.

20. The semiconductor structure of claim 1 , wherein the molding material has a first surface facing with the second redistribution structure, wherein the semiconductor structure further comprises a dielectric film between the second redistribution structure and the dummy metal layer, the dielectric film having a same width with the die, and a first surface of the dielectric film facing the die being closer to the die than the first surface of the molding material, wherein the thermally conductive material extends through the dielectric film.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Pei Hao-Jan
• Chen Wei-Yu
• Cheng Chia-Shen
• Tsao Chih-Chiang
• Chen Cheng-Ting
• Chang Chia-Lun
• Lin Chih-Wei
• Lin Hsiu-Jen
• Hsieh Ching-Hua
• Liu Chung-Shi

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title