Wire bond support structure and microelectronic package including wire bonds therefrom

Patent metadata

Field	Value
Publication number	US-9412714-B2
Application number	US-201414291874-A
Country	US
Kind code	B2
Filing date	May 30, 2014
Priority date	May 30, 2014
Publication date	Aug 9, 2016
Grant date	Aug 9, 2016

Abstract

A microelectronic package may include a substrate having first and second regions, a first surface and a second surface remote from the first surface; at least one microelectronic element overlying the first surface within the first region; electrically conductive elements at the first surface within the second region; a support structure having a third surface and a fourth surface remote from the third surface and overlying the first surface within the second region in which the third surface faces the first surface, second and third electrically conductive elements exposed respectively at the third and fourth surfaces and electrically connected to the conductive elements at the first surface in the first region; and wire bonds defining edge surfaces and having bases electrically connected through ones of the third conductive elements to respective ones of the second conductive elements and ends remote from the support structure and the bases.

First claim

The invention claimed is:

1. A microelectronic package comprising:
a substrate having a first surface and a second surface remote from the first surface;
at least one microelectronic element overlying a portion of the first surface, thereby defining a first region thereof, wherein a second region of the first surface is defined by another portion of the first surface disposed beyond the at least one microelectronic element;
electrically conductive elements at the first surface of the substrate within the second region;
a support structure having a third surface and a fourth surface remote from the third surface, the support structure overlying the second region of the first surface and not overlying the first region of the first surface, wherein the third surface faces the first surface, the support structure having second and third electrically conductive elements exposed respectively at the third and fourth surfaces, the second electrically conductive elements being electrically connected to the conductive elements at the first surface of the substrate in the first region; and
wire bonds defining edge surfaces and having bases electrically connected through ones of the third conductive elements to respective ones of the second conductive elements and ends remote from the support structure and the bases,
an integral continuous encapsulation region contacting the support structure, the substrate and at least edge surfaces of the wire bonds.

2. The microelectronic package of claim 1
wherein the encapsulation region extends from the first surface and covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation region, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends.

3. The microelectronic package of claim 1 further comprising:
a redistribution layer extending along at least a portion of at least one of the third surface or the fourth surface,
wherein the redistribution layer includes a redistribution substrate having a fifth surface adjacent the least one of the third surface or the fourth surface and a sixth surface remote from the fifth surface, first electrically conductive pads at the fifth surface of the redistribution substrate aligned with and contacting respective ones of the second or third electrically conductive elements at the third or fourth surfaces, and second electrically conductive pads at the sixth surface of the redistribution substrate electrically connected to the first conductive pads.

4. The microelectronic package of claim 1 , wherein the second conductive elements are bonded to respective ones of the conductive elements at the first surface of the substrate by a conductive bonding material.

5. The microelectronic package of claim 1 , wherein conductive vias of the support structure electrically connect ones of the bases of the wire bonds with respective ones of the second conductive elements at the third surface of the support structure.

6. The microelectronic package of claim 1 , wherein the encapsulation region encapsulates the at least one microelectronic element.

7. The microelectronic package of claim 1 , wherein the encapsulation region has a major surface remote from the first surface of the substrate, and ends of the wire bonds project above the major surface of the encapsulation region.

8. The microelectronic package of claim 1 , wherein the support structure is in form of a frame surrounding an open, interior region having dimensions sufficient to receive the at least one microelectronic element therein.

9. The microelectronic package of claim 8 , wherein the support structure surrounds the at least one microelectronic element.

10. The microelectronic package of claim 9 , wherein the encapsulation region entirely covers the fourth surface of the support structure and the wire bonds extend through the encapsulation region.

Assignees

• Invensas Corp

Inventors

• Co Reynaldo
• Zohni Wael
• Saga Cizek Rizza Lee
• Katkar Rajesh

Classifications

• H10P72/7412

  the auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support · CPC title

• H10P72/744

  Details of chemical or physical process used for separating the auxiliary support from a device or a wafer · CPC title

• H10P72/743

  used as a support during manufacture of interconnect decals or build up layers · CPC title

• H10P72/74

  using temporarily an auxiliary support · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title