Semiconductor structure and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9543373-B2
Application number	US-201314061615-A
Country	US
Kind code	B2
Filing date	Oct 23, 2013
Priority date	Oct 23, 2013
Publication date	Jan 10, 2017
Grant date	Jan 10, 2017

Abstract

A semiconductor structure includes a three dimensional stack including a first semiconductor die and a second semiconductor die. The second semiconductor die is connected with the first semiconductor die with a bump between the first semiconductor die and the second semiconductor die. The semiconductor structure includes a molding compound between the first semiconductor die and the second semiconductor die. A first portion of a metal structure over a surface of the three dimensional stack and contacting a backside of the second semiconductor die and a second portion of the metal structure over the surface of the three dimensional stack and configured for electrically connecting the three dimensional stack with an external electronic device.

First claim

What is claimed is:

1. A semiconductor structure, comprising:
a substrate and a first circuit on the substrate;
a metal structure comprising an active portion and a dummy portion, the active portion electrically coupled with the first circuit through a conductive plug, the dummy portion not being electrically coupled with any circuitry, the active portion and the dummy portion being on a same level of the metal structure;
a semiconductor die bonded to the substrate through a first active bump via a conductive pad on an active surface of the semiconductor die, a passive surface of the semiconductor die contacting the dummy portion of the metal structure, wherein the passive surface is opposite to the active surface;
a dummy bump connected to the dummy portion of the metal structure; and
a molding compound between the substrate and the active surface of the semiconductor die and surrounding the conductive plug;
wherein the dummy bump is surrounded by ambient air.

2. The semiconductor structure of claim 1 , wherein the dummy bump is configured to dissipate heat from the passive surface.

3. The semiconductor structure of claim 1 , wherein the active portion of the metal structure further comprises a redistribution layer (RDL) connecting to one end of the conductive plug.

4. The semiconductor structure of claim 1 , wherein the dummy portion of the metal structure further comprises an under bump metal (UBM) for receiving the dummy bump.

5. The semiconductor structure of claim 1 , further comprising a second active bump connected to the active portion of the metal structure.

6. The semiconductor structure of claim 1 , wherein the first circuit circuitry includes a post passivation inductor (PPI).

7. The semiconductor structure of claim 6 , wherein the PPI is connected to one end of the conductive plug.

8. The semiconductor structure of claim 1 , wherein the conductive pad is an under bump metal (UBM), and the conductive pad is connected to an interconnection of the semiconductor die.

9. The semiconductor structure of claim 1 , wherein the substrate includes a semiconductor device.

10. A semiconductor structure, comprising:
a three dimensional stack comprising:
a first semiconductor die;
a second semiconductor die electrically connected with the first semiconductor die with a first active bump positioned on a frontside of the second semiconductor die; and
a molding compound between the first semiconductor die and the second semiconductor die;
wherein a dummy portion of a metal structure being over a surface of the three dimensional stack and contacting a backside of the second semiconductor die, the dummy portion neither being electrically coupled to the first semiconductor die nor to the second semiconductor die;

a dummy bump connected with the dummy portion of the metal structure, the dummy bump being surrounded by ambient air; and
an active portion of the metal structure over the surface of the three dimensional stack, not contacting the backside of the second semiconductor die, and configured for electrically connecting the three dimensional stack with an external electronic device, wherein the active portion and the dummy portion are in a same level of the metal structure.

11. The semiconductor structure of claim 10 , further comprising a conductive plug between the active portion of the metal structure and the first semiconductor die.

12. The semiconductor structure of claim 10 , wherein the dummy bump is configured to connect with a dummy pattern external to the three dimensional stack.

13. The semiconductor structure of claim 10 , further comprising a PPI on the first semiconductor die and electrically coupled to the first semiconductor die.

14. The semiconductor structure of claim 1 , wherein the metal structure further comprises a redistribution layer (RDL) connecting to the passive surface of the semiconductor die.

15. The semiconductor structure of claim 1 , further comprising a dummy bump connected to the dummy portion of the metal structure, wherein the dummy bump comprises a three dimensional surface.

16. The semiconductor structure of Claim 3 , wherein the passive surface of the semiconductor die is contacting a bottom of a recess of the RDL.

17. The semiconductor structure of claim 6 , wherein the PPI is electrically connected to the active surface of the semiconductor die.

18. The semiconductor structure of claim 12 , wherein the dummy pattern is electrically connected to a redistribution layer (RDL).

19. The semiconductor structure of claim 18 , wherein a recess portion of the RDL is contacting the backside of the second semiconductor die.

20. The semiconductor structure of claim 10 , further comprising a PPI on the first semiconductor die and electrically coupled to the active portion of the metal structure.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liang Shih-Wei
• Pan Hsin-Yu
• Wu Kai-Chiang
• Yang Ching-Feng
• Liu Ming-Kai
• Miao Chia-Chun

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title

• H10W72/823

  Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip · CPC title