Indium gallium arsenide metal oxide semiconductor field effect transistor having a low contact resistance to metal electrode

Patent metadata

Field	Value
Publication number	US-10559669-B2
Application number	US-201916353332-A
Country	US
Kind code	B2
Filing date	Mar 14, 2019
Priority date	Dec 27, 2017
Publication date	Feb 11, 2020
Grant date	Feb 11, 2020

Abstract

A semiconductor device that includes source and drain regions that are doped to an n-type conductivity and are comprised of a type III-V semiconductor material. The semiconductor device further includes a contact to at least one of the source and drain regions. The contact includes an interface passivation layer atop the at least one source and drain region, and an n-type zinc oxide layer. A conduction band of the type III-V semiconductor material of the at least one source and drain region is substantially aligned with a conduction band of the n-type zinc oxide containing layer.

First claim

What is claimed is:

1. A method of forming a semiconductor device comprising:
providing a field effect transistor including a region composed of a type III-V semiconductor material and an n-type conductivity;
forming at least one of sulfur passivation layer and an aluminum containing layer on an interface surface of the at least one of the type III-V semiconductor material to provide a passivated surface;
forming an n-type zinc oxide containing layer on the passivated surface; and
forming a metal contact on the n-type zinc oxide containing layer.

2. The method of claim 1 , wherein the type III-V semiconductor material is indium gallium arsenide (InGaAs).

3. The method of claim 1 , wherein a channel region of the field effect transistor comprises indium gallium arsenide (InGaAs).

4. The method of claim 1 , wherein the sulfur passivation layer is formed by applying a thiourea containing solution.

5. The method of claim 4 , wherein the sulfur passivation layer is a monolayer in thickness.

6. The method of claim 1 , wherein the aluminum containing layer comprises aluminum oxide formed by atomic layer deposition (ALD).

7. The method of claim 5 , wherein the aluminum containing layer is a monolayer in thickness.

8. The method of claim 1 , wherein the n-type zinc oxide containing layer is formed by atomic layer deposition.

9. The method of claim 1 , wherein the metal contact is composed of a composition selected from aluminum, titanium, and combinations thereof.

10. The method of claim 1 , wherein a conduction band of the type III-V semiconductor material is substantially aligned with a conduction band of the n-type zinc oxide containing layer.

11. A method of forming a semiconductor device comprising:
providing a field effect transistor including a region composed of indium gallium arsenide (InGaAs) doped to an n-type conductivity;
forming at least one of sulfur passivation layer and an aluminum containing layer on an interface surface the region of the type III-V semiconductor material to provide a passivated surface;
forming an n-type zinc oxide containing layer on the passivated surface, wherein a conduction band of the InGaAs is substantially aligned with a conduction band of the n-type zinc oxide containing layer; and
forming a metal contact is formed on the n-type zinc oxide containing layer.

12. The method of claim 11 , wherein a channel region of the field effect transistor comprises indium gallium arsenide (InGaAs).

13. The method of claim 11 , wherein the sulfur passivation layer is formed by applying a thiourea containing solution.

14. The method of claim 11 , wherein the aluminum containing layer comprises aluminum oxide formed by atomic layer deposition (ALD).

15. A semiconductor device comprising:
an n-type conductivity region comprised of a type III-V semiconductor material; and
a contact to the n-type conductivity region, wherein the contact comprises an interface passivation layer atop the type III-V semiconductor material, and an n-type zinc oxide layer, wherein a conduction band of the type III-V semiconductor material is substantially aligned with a conduction band of the n-type zinc oxide containing layer.

16. The semiconductor device of claim 15 , wherein the contact may further include a metal containing portion on the n-type zinc oxide containing layer.

17. The semiconductor device of claim 16 , wherein the metal contact is composed of a composition selected from aluminum, titanium, and combinations thereof.

18. The semiconductor device of claim 15 , wherein the type III-V semiconductor material is indium gallium arsenide (InGaAs).

19. The semiconductor device of claim 15 , wherein the interface passivation layer includes a sulfur passivation layer.

20. The semiconductor device of claim 15 , wherein the interface passivation layer includes an aluminum oxide monolayer.

Assignees

• IBM

Inventors

• Li Ning
• Lee Yun Seog
• De Souza Joel P
• Sadana Devendra K

Classifications

• H10P70/234

  the processing being the formation of vias or contact holes · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10P14/69391

  the material containing aluminium, e.g. Al2O3 · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10P14/3442

  N-type · CPC title