Devices with an array of superconducting logic cells

Patent metadata

Field	Value
Publication number	US-9712172-B2
Application number	US-201514877550-A
Country	US
Kind code	B2
Filing date	Oct 7, 2015
Priority date	Oct 7, 2015
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

A device including an array of superconducting logic cells, where each of the superconducting logic cells is configured to receive at least one input and provide at least one output, is provided. Each of the superconducting logic cells includes at least one Josephson junction, whose state changes based on at least a biasing condition caused by a phase of a first clock or a phase of a second clock. The array of the superconducting logic cells is configured to perform at least one operation based at least on a connection arrangement of the array of the superconducting logic cells.

First claim

What is claimed:

1. A device comprising:
a first clock terminal for receiving a first clock having a first phase;
a second clock terminal for receiving a second clock having a second phase different from the first phase; and
an array of superconducting logic cells, wherein each of the superconducting logic cells is configured to receive at least one input and provide at least one output, and wherein each of the superconducting logic cells comprises at least one Josephson junction configured to change its state based on at least one of: (1) a first biasing condition caused by the first phase of the first clock or (2) a second biasing condition caused by the second phase of the second clock, and wherein each of the superconducting logic cells is arranged in a pre-determined location in the array, and wherein a first set of the superconducting logic cells in the array of the superconducting logic cells is configured to process at least a first set of inputs during the first phase of the first clock at least in response to the first biasing condition to generate a first set of outputs and a second subset of the superconducting logic cells in the array of superconducting logic cells is configured to process at least a second set of inputs during the second phase of the second clock at least in response to the second biasing condition, and wherein the array of the superconducting cells is configured to perform at least one operation by processing at least one of the first set of inputs and the second set of inputs, and wherein the at least one operation is performed based on a connection arrangement of the array of superconducting logic cells, wherein with respect to connections with other superconducting logic cells in the array of the superconducting logic cells, each of the superconducting logic cells is connected only to adjacent superconducting logic cells in the array of the superconducting logic cells, and wherein each of the superconducting logic cells comprises a gate selected from a group consisting of an AND gate, an OR gate, and an AanB gate.

2. The device of claim 1 , wherein the device is configured as a programmable logic array.

3. The device of claim 1 , wherein with respect to the connections with the other superconducting logic cells in the array of the superconducting logic cells, each of the connections is formed via an abutment.

4. The device of claim 1 , wherein each of the superconducting logic cells is formed using reciprocal quantum logic circuits.

5. The device of claim 1 , wherein the device is configured as a decoder.

6. The device of claim 1 , wherein the first set of the inputs and the second set of the inputs comprise at least one of a plurality of inverted terms or a plurality of non-inverted terms, and the device further comprising a first signal line for consolidating the plurality of the non-inverted terms and a second signal line for consolidating the plurality of the inverted terms.

7. A device comprising:
a first clock terminal for receiving a first clock having a first phase;
a second clock terminal for receiving a second clock having a second phase different from the first phase;
an input terminal for receiving a logic high signal; and
an array of superconducting logic cells, wherein each of the superconducting logic cells is configured to receive at least one input and provide at least one output, and wherein each of the superconducting logic cells comprises at least one Josephson junction configured to change its state based on at least one of: (1) a first biasing condition caused by the first phase of the first clock or (2) a second biasing condition caused by the second phase of the second clock, and wherein each of the superconducting logic cells is arranged in a pre-determined location in the array, and wherein a first set of the superconducting logic cells in the array of the superconducting logic cells is configured to process at least a first set of inputs during the first phase of the first clock at least in response to the first biasing condition to generate a first set of outputs and a second subset of the superconducting logic cells in the array of superconducting logic cells is configured to process at least a second set of inputs during the second phase of the second clock at least in response to the second biasing condition, and wherein the first set of inputs and the second set of inputs comprise at least one of a plurality of inverted terms or a plurality of non-inverted terms, and wherein, based on a connection arrangement of the array of the superconducting logic cells, the plurality of the inverted terms are combined using a logical OR operation and the plurality of the non-inverted terms and the logic high signal are combined using a logical AND operation.

8. The device of claim 7 , wherein with respect to connections with other superconducting logic cells in the array of the superconducting logic cells, each of the superconducting logic cells is connected only to directly adjacent superconducting logic cells in the array of the superconducting logic cells.

9. The device of claim 8 , wherein with respect to the connections with the other superconducting logic cells in the array of the superconducting logic cells, each of the connections is formed via an abutment.

10. The device of claim 7 further comprising a first signal line for consolidating the non-inverted terms and a second signal line for consolidating the inverted terms.

11. The device of claim 7 , wherein the device is configured as a programmable logic array.

12. The device of claim 7 , wherein each of the superconducting logic cells is formed using reciprocal quantum logic circuits.

13. The device of claim 7 , wherein the device is configured as a decoder.

14. A method in a device comprising a first clock terminal for receiving a first clock having a first phase, a second clock terminal for receiving a second clock having a second phase different from the first phase, and an array of superconducting logic cells, wherein each of the superconducting logic cells is configured to receive at least one input and provide at least one output, and wherein each of the superconducting logic cells comprises at least one Josephson junction configured to change its state based on at least one of: (1) a first biasing condition caused by the first phase of the first clock or (2) a second biasing condition caused by the second phase of the second clock, and wherein each of the superconducting logic cells is arranged in a pre-determined location in the array, the method comprising:
processing, using a first subset of the superconducting logic cells in the array of superconducting logic cells, at least a first set of inputs during the first phase of the first clock at least in response to the first biasing condition to generate a first set of outputs;
processing, using a second subset of the superconducting logic cells in the array of superconducting logic cells, at least a second set of inputs during the second phase of the second clock at least in response to the second biasing condition;
performing at least one logical operation by processing at least one of the first set of inputs and the second set of inputs, wherein the first set of inputs and the second set of inputs may include at least one of a plurality of inverted terms or a plurality of non-inverted terms, and wherein the performing the at least one logical operation further comprises combining the plurality of inverted terms using at least one OR gate and combining the plurality of non-inverted terms using at least one AND gate to generate at least one product term; and
outputting the

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Shauck Steven B
• Braun Alexander

Classifications

• H03K19/195 Primary

  using superconductive devices · CPC title

• H03K19/0008

  Arrangements for reducing power consumption · CPC title

• H03K19/17708

  using an AND matrix followed by an OR matrix, i.e. programmable logic arrays · CPC title

• G06N99/002

  Physics · mapped topic

• H03K19/17724

  Structural details of logic blocks · CPC title