Superconducting gate memory circuit

Patent metadata

Field	Value
Publication number	US-9812192-B1
Application number	US-201615351065-A
Country	US
Kind code	B1
Filing date	Nov 14, 2016
Priority date	Sep 2, 2016
Publication date	Nov 7, 2017
Grant date	Nov 7, 2017

Abstract

One embodiment includes a superconducting gate memory circuit. The circuit includes a Josephson D-gate circuit configured to set a digital state as one of a first data state and a second data state in response to a write enable single flux quantum (SFQ) pulse provided on a write enable input and a respective presence of or absence of a write data SFQ pulse provided on a data write input. The circuit also includes a storage loop coupled to the Josephson D-gate. The storage loop can be configured to store the digital state and to readout the digital state at an output in response to a read enable SFQ pulse provided on a read enable input and a read data SFQ pulse provided on a read data input.

First claim

What is claimed is:

1. A superconducting gate memory circuit comprising:
a Josephson D-gate circuit configured to set a digital state as one of a first data state and a second data state in response to a write enable single flux quantum (SFQ) pulse provided on a write enable input and a respective presence of or absence of a write data SFQ pulse provided on a data write input; and
a storage loop coupled to the Josephson D-gate, the storage loop being configured to store the digital state and to readout the digital state at an output in response to a read enable SFQ pulse provided on a read enable input and a read data SFQ pulse provided on a read data input.

2. The circuit of claim 1 , wherein the storage loop is configured to conduct a loop current having an amplitude that is set by the Josephson D-gate circuit, the storage loop comprising a readout Josephson junction that is configured to trigger or not trigger in response to the read enable SFQ pulse and the read data SFQ pulse to indicate the respective first data state or second data state at the output based on an amplitude of the loop current.

3. The circuit of claim 2 , wherein the Josephson D-gate comprises a first Josephson junction associated with the write enable input and a second Josephson junction associated with the write data input, wherein the digital state corresponds to a superconducting phase associated with the first Josephson junction.

4. The circuit of claim 3 , wherein the Josephson D-gate is configured to set the digital state from the first data state to the second data state based on setting the first Josephson junction to a 2π-state in response to the write enable SFQ pulse and the write data SFQ pulse, the 2π-state of the first Josephson junction providing the superconducting phase at a non-zero amplitude that is inductively coupled to the storage loop to set the amplitude of the loop current to correspond to the second data state.

5. The circuit of claim 3 , wherein the Josephson D-gate circuit further comprises a bias transformer, the bias transformer comprising:
a primary inductor configured to conduct a bias current;
a secondary inductor interconnecting the first and second Josephson junctions and being configured to conduct an induced bias current in the first and second Josephson junctions in response to the bias current, wherein the storage loop comprises a tertiary inductor associated with the bias transformer that is configured to inductively couple the superconducting phase into the storage loop to affect the amplitude of the loop current.

6. The circuit of claim 2 , wherein the storage loop comprises at least one loop transformer, each of the at least one loop transformer comprises:
a primary inductor configured to conduct a bias current;
a secondary inductor in series with the readout Josephson junction and being configured to induce the loop current, such that the loop current has a first amplitude corresponding to the first data state, and a second amplitude that is set by the Josephson D-gate corresponding to the second data state.

7. The circuit of claim 6 , wherein one of the at least one loop transformer further comprises a tertiary inductor that is inductively coupled to the primary inductor associated with the respective at least one loop transformer, the tertiary inductor being configured to conduct the read enable SFQ pulse to change the amplitude of the loop current to bias the readout Josephson junction.

8. The circuit of claim 6 , wherein the storage loop is configured to receive the read data SFQ pulse Josephson to trigger the readout Josephson junction in response to the loop current having the second amplitude, or to not trigger the readout Josephson junction in response to the loop current having the first amplitude.

9. The circuit of claim 6 , wherein the second amplitude of the loop current is approximately equal to the first amplitude of the loop current minus an induced current component corresponding to a superconducting phase of at least one Josephson junction associated with the Josephson D-gate that that is induced in the storage loop.

10. A memory cell comprising the superconducting gate memory circuit of claim 1 , the memory cell further comprising:
a first Josephson transmission line (JTL) interconnect that couples a word-write line to the write enable input to provide the write enable SFQ pulse based on a word-write signal that propagates on the word-write line;
a second JTL interconnect that couples a bit-write line to the write data input to provide the write data SFQ pulse based on a bit-write signal that propagates on the bit-write line;
a third JTL interconnect that couples a word-read line to the read enable input to provide the read enable SFQ pulse based on a word-read signal that propagates on the word-read line; and
a fourth JTL interconnect that couples a bit-read line to the read data input to provide the read data SFQ pulse based on a bit-read signal that propagates on the bit-read line.

11. A superconducting memory circuit comprising a plurality of memory cells of claim 10 arranged in an array of a plurality of rows and a plurality of columns, wherein the word-write line is one of a respective plurality of word-write lines configured to select a respective one of plurality of rows and wherein the bit-write line is one of a respective plurality of bit-write lines configured to write data into a set of the plurality of memory cells corresponding to the selected one of the plurality of rows during a data write operation, and wherein the word-read line is one of a respective plurality of word-read lines configured to select a respective one of plurality of rows and wherein the bit-read line is one of a respective plurality of bit-read lines configured to read data from a set of the plurality of memory cells corresponding to the selected one of the plurality of rows during a data read operation.

12. A method for reading a digital state from a superconducting gate memory circuit, the method comprising:
storing the digital state as one of a first data state and a second data state via a Josephson D-gate to conduct a loop current associated with a storage loop comprising a readout Josephson junction and an output, the loop current having an amplitude that is based on digital state;
providing a read enable single flux quantum (SFQ) pulse on a read enable input to bias the readout Josephson junction; and providing a read data SFQ pulse on a read data input to trigger or not trigger the readout Josephson junction in response to the read data SFQ pulse to indicate the respective first data state or second data state at the output based on the amplitude of the loop current.

13. The method of claim 12 , further comprising providing a bias current to at least one loop transformer, each of the at least one loop transformer comprising a primary inductor configured to conduct the bias current and a secondary inductor in series with the readout Josephson junction and being configured to induce the loop current, such that the loop current has a first amplitude corresponding to the first data state, and a second amplitude that is set by the Josephson D-gate corresponding to the second data state.

14. The method of claim 13 , wherein one of the at least one loop transformer further comprises a tertiary inductor that is inductively coupled to the primary inductor associated with the respective at least one loop transformer, wherein providing the read enable SFQ pulse comprises providing the read enable SFQ pulse to the tertiary inductor to change the amplitude of the loop current to bias the readout Josephson junction.

Assignees

• Burnett Randall M
• Herr Quentin P
• Northrop Grumman Systems Corp

Inventors

• Burnett Randall M
• Herr Quentin P

Classifications

• H03K19/195

  using superconductive devices · CPC title

• H03K3/38

  by the use, as active elements, of superconductive devices · CPC title

• G11C11/44 Primary

  using super-conductive elements, e.g. cryotron · CPC title