Memory device

Patent metadata

Field	Value
Publication number	US-9953999-B2
Application number	US-201615375944-A
Country	US
Kind code	B2
Filing date	Dec 12, 2016
Priority date	Jul 19, 2016
Publication date	Apr 24, 2018
Grant date	Apr 24, 2018

Abstract

In one embodiment, the semiconductor device includes a stack of alternating first interlayer insulating layers and gate electrode layers on a substrate. At least one of the gate electrode layers has a first portion and a second portion. The second portion forms an end portion of the at least one gate electrode layer, and a bottom surface of the second portion is at a lower level than a bottom surface of the first portion. A contact plug extends from the second portion.

First claim

We claim:

1. A semiconductor device, comprising:
a stack of alternating first interlayer insulating layers and gate electrode layers on a substrate, at least one of the gate electrode layers having a first portion and a second portion, the second portion forming an end portion of the at least one gate electrode layer, and a bottom surface of the second portion being at a lower level than a bottom surface of the first portion; and
a contact plug extending from the second portion,
wherein an end of the second portion has a concave profile.

2. The semiconductor device of claim 1 , wherein the at least one gate electrode layer curves convexly from the bottom surface of the first portion to the bottom surface of the second portion.

3. The semiconductor device of claim 2 , wherein the second portion curves convexly from a bottom surface to an end of the second portion.

4. The semiconductor device of claim 1 , wherein the second portion curves convexly from a bottom surface to an end of the second portion.

5. The semiconductor device of claim 1 , wherein an end of the second portion has a half bullnose shape.

6. The semiconductor device of claim 1 , wherein a top surface of the second portion is at a higher level than a top surface of the first portion.

7. The semiconductor device of claim 6 , wherein a first difference between a level of the bottom surface of the second portion and a level of the bottom surface of the first portion is greater than a second difference between a level of the top surface of the second portion and a level of the top surface of the first portion.

8. The semiconductor device of claim 6 , wherein an end of the second portion has a full bullnose shape.

9. The semiconductor device of claim 6 , wherein the at least one gate electrode layer curves convexly from the bottom surface of the first portion to the bottom surface of the second portion, and the at least one gate electrode layer curves convexly from the top surface of the first portion to the top surface of the second portion.

10. The semiconductor device of claim 6 , further comprising:
a second interlayer insulating layer over the stack; and wherein
the contact plug extends through the second interlayer insulating layer.

11. The semiconductor device of claim 10 , wherein a portion of the second interlayer insulating layer at the second portion include impurities, and a portion of the first interlayer insulating layers directly above and directly below the second portion include the impurities.

12. The semiconductor device of claim 1 , further comprising:
a second interlayer insulating layer over the stack; and wherein
the contact plug extends through the second interlayer insulating layer.

13. The semiconductor device of claim 12 , wherein a portion of the second interlayer insulating layer at the second portion include impurities, and a portion of the first interlayer insulating layer directly below the second portion includes the impurities.

14. A semiconductor device, comprising:
a stack of alternating interlayer insulating layers and gate electrode layers on a substrate, at least one of the gate electrode layers having a first portion and second portion, the second portion forming an end portion of the at least one gate electrode layer, and a bottom surface of the second portion being closer to the substrate than a bottom surface of the first portion; and
a contact plug extending from the second portion,
wherein an end of the second portion has a concave profile.

15. A semiconductor device, comprising:
a stack of alternating interlayer insulating layers and gate electrode layers on a substrate, at least one of the gate electrode layers having a first portion and second portion, the second portion forming an end of the at least one gate electrode layer, and as the at least one gate electrode layer transitions from the first portion to the second portion, the at least one gate electrode layer projects towards the substrate; and
a contact plug extending from the second portion,
wherein an end of the second portion has a concave profile.

16. The semiconductor device of claim 15 , wherein a thickness of the second portion is greater than a thickness of the first portion.

17. The semiconductor device of claim 15 , wherein a bottom surface of the second portion is closer to the substrate than a bottom surface of the first portion.

18. The semiconductor device of claim 15 , wherein an upper surface of the second portion is farther from the substrate than an upper surface of the first portion.

Assignees

• Nam Phil Ouk
• Kim Sung Gil
• Kim Seulye
• Kim Hong Suk
• Ahn Jae Young
• Choi Ji Hoon
• Samsung Electronics Co Ltd

Inventors

• Nam Phil Ouk
• Kim Sung Gil
• Kim Seulye
• Kim Hong Suk
• Ahn Jae Young
• Choi Ji Hoon

Classifications

• H01L27/11556

  Electricity · mapped topic

• H01L27/11565

  Electricity · mapped topic

• H01L29/4234

  Electricity · mapped topic

• H01L29/42324

  Electricity · mapped topic

• H01L27/11519

  Electricity · mapped topic