Nonvolatile memory devices having vertically integrated nonvolatile memory cell sub-strings therein

Patent metadata

Field	Value
Publication number	US-9000508-B2
Application number	US-201314024844-A
Country	US
Kind code	B2
Filing date	Sep 12, 2013
Priority date	Jul 2, 2010
Publication date	Apr 7, 2015
Grant date	Apr 7, 2015

Abstract

Nonvolatile memory devices according to embodiments of the invention include highly integrated vertical stacks of nonvolatile memory cells. These vertical stacks of memory cells can utilize dummy memory cells to compensate for process artifacts that would otherwise yield relatively poor functioning memory cell strings when relatively large numbers of memory cells are stacked vertically on a semiconductor substrate using a plurality of vertical sub-strings electrically connected in series.

First claim

That which is claimed is:

1. A nonvolatile memory device, comprising:
a first stack of layers on a substrate, said first stack of layers comprising first interlayer dielectric layers and first word lines arranged vertically in an alternating sequence;
a first active region penetrating the first stack of layers;
a second stack of layers on the first stack of layers, said second stack of layers comprising second interlayer dielectric layers and second word lines arranged vertically in an alternating sequence;
a second active region penetrating the second stack of layers, contacting the first active region; and
a dummy word line disposed adjacent to a contact position in which the first active region and the second active region contact each other.

2. The device of claim 1 , wherein the second active region is electrically coupled to the first active region.

3. The device of claim 1 , wherein a lower surface of the second active region is lower than an upper surface of the first active region.

4. The device of claim 1 , wherein a width of an upper portion of the first active region is greater than a width of a lower portion of the second active region.

5. The device of claim 4 , wherein the first active region has a cup shape, and an inner surface of the first active region contacts an outer surface of the upper portion of the second active region.

6. The device of claim 1 , wherein an upper surface of the first active region is lower than an upper surface of an interlayer dielectric layer immediately above the dummy word line.

7. The device of claim 6 , wherein the upper surface of the first active region is lower than an upper surface of the dummy word line.

8. The device of claim 1 , wherein a lower surface of the second active region is higher than a lower surface of an interlayer dielectric layer immediately below the dummy word line.

9. The device of claim 8 , wherein the lower surface of the second active region is higher than a lower surface of the dummy word line.

10. The device of claim 1 , wherein a height of an upper surface of the first active region is between an uppermost first word line and a lowermost second word line.

11. The device of claim 10 , wherein a height of a lower surface of the second active region is between the uppermost first word line and the lowermost second word line.

12. The device of claim 10 , wherein the dummy word line is between the uppermost first word line and the lowermost second word line.

13. The device of claim 1 , wherein the dummy word line covers both of an upper portion of the first active region and a lower portion of the second active region.

14. The device of claim 13 , wherein the dummy word line comprises a protrusion portion that protrudes from a first surface facing an outer surface of the upper portion of the first active region toward an outer surface of the lower portion of the second active region, and wherein the protrusion portion is thinner than the dummy word line.

15. The device of claim 13 , wherein an outer surface of the first active region and the second active region has a stepped profile proximate the contact position, and wherein the dummy word line covers the stepped profile.

16. The device of claim 1 , wherein the dummy word line comprises a first dummy word line and a second dummy word line, and an outer surface of the first active region and the second active region has a stepped profile near the contact position,
wherein the first dummy word line covers the first active region, and the second dummy word line covers the stepped profile.

17. The device of claim 16 , wherein the dummy word line further comprises a third dummy word line, and the third dummy word line covers the second active region.

18. The device of claim 1 , further comprising an information storage layer between the first and second active regions and the first, second and dummy word lines.

19. The device of claim 17 , wherein the information storage layer extends between the first, second and dummy word lines and the first and second interlayer dielectric layers.

20. The device of claim 18 , wherein the information storage layer extends between the first and second active regions and the first and second interlayer dielectric layers.

21. The device of claim 1 , wherein an upper portion of the first active region has an impurity region doped with a different type than the first active region.

22. The device of claim 1 , further comprising an active pattern contacting an inner surface of the first active region and a lower surface of the second active region.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Changhyun
• Shim Sunhil
• Jang Jaehoon
• Hur Sunghoi
• Kim Hansoo
• Kim Kihyun

Classifications

• H10D30/693

  Vertical IGFETs having charge trapping gate insulators · CPC title

• H10D30/689 Primary

  Vertical floating-gate IGFETs · CPC title

• H10D88/00

  Three-dimensional [3D] integrated devices · CPC title

• H01L27/11578

  Electricity · mapped topic

• H01L29/7926

  Electricity · mapped topic