Vertical NAND and method of making thereof using sequential stack etching and self-aligned landing pad

Patent metadata

Field	Value
Publication number	US-9698153-B2
Application number	US-201615080269-A
Country	US
Kind code	B2
Filing date	Mar 24, 2016
Priority date	Mar 12, 2013
Publication date	Jul 4, 2017
Grant date	Jul 4, 2017

Abstract

Alignment between memory openings through multiple tier structures can be facilitated employing a temporary landing pad. The temporary landing pad can have a greater area than the horizontal cross-sectional area of a first memory opening through a first tier structure including a first alternating stack of first insulating layers and first spacer material layers. An upper portion of a first memory film is removed, and a sidewall of an insulating cap layer that defines the first memory opening can be laterally recessed to form a recessed cavity. A sacrificial fill material is deposited in the recessed cavity to form a sacrificial fill material portion, which functions as the temporary landing pad for a second memory opening that is subsequently formed through a second tier structure including second insulating layers and second spacer material layers. A memory stack structure can be formed through the first and second tier structures.

First claim

What is claimed is:

1. A monolithic three-dimensional memory device comprising:
a first tier structure located over a top surface of a substrate and comprising a first alternating stack of first insulating layers and first electrically conductive layers;
an insulating cap layer overlying the first tier structure;
a second tier structure located over the insulating cap layer and comprising a second alternating stack of second insulating layers and second electrically conductive layers; and
a memory stack structure comprising a first memory film located within the first tier structure, a second memory film located within the second tier structure, and a semiconductor channel that extends through the second tier structure, the insulating cap layer, and the first tier structure, wherein the semiconductor channel contacts the insulating cap layer.

2. The monolithic three-dimensional memory device of claim 1 , wherein the semiconductor channel is laterally spaced from the first tier structure by the first memory film, and is laterally spaced from the second tier structure by the second memory film.

3. The monolithic three-dimensional memory device of claim 1 , wherein the first memory film is vertically spaced from the second memory film by a laterally protruding portion of the semiconductor channel such that the first memory film does not contact the second memory film.

4. The monolithic three-dimensional memory device of claim 3 , wherein the laterally protruding portion of the semiconductor channel comprises a convex sidewall in physical contact with a concave sidewall of the insulating cap layer and an annular rim which surrounds a bottom portion of the second memory film and contacts the insulating cap layer.

5. The monolithic three-dimensional memory device of claim 3 , wherein the laterally protruding portion of the semiconductor channel protrudes farther outward than outer sidewalls of the first memory film and the second memory film.

6. The monolithic three-dimensional memory device of claim 1 , wherein a first horizontal portion of the semiconductor channel is in contact with a horizontal annular bottom surface of the second memory film.

7. The monolithic three-dimensional memory device of claim 6 , wherein a second horizontal portion of the semiconductor channel is in contact with an annular top surface of the first memory film.

8. The monolithic three-dimensional memory device of claim 1 , wherein each of the first and second memory films comprises:
a tunneling dielectric layer laterally surrounding the semiconductor channel;
a plurality of charge storage regions located outside of the tunneling dielectric layer; and
a blocking dielectric layer laterally surrounding a respective plurality of charge storage regions.

9. The monolithic three-dimensional memory device of claim 1 , further comprising a dielectric core located within the semiconductor channel and comprising a laterally protruding portion that laterally extends farther outward than a first portion of the dielectric core surrounded by the first memory film and a second portion of the dielectric core surrounded by the second memory film.

10. The monolithic three-dimensional memory device of claim 1 , wherein the dielectric core comprises a neck portion adjoined to the laterally protruding portion and having a lesser lateral extent than the first portion of the dielectric core and the second portion of the dielectric core.

11. The monolithic three-dimensional memory device of claim 1 , wherein:
the monolithic three-dimensional memory device comprises a monolithic three-dimensional NAND memory device;
the first and second electrically conductive layers comprise, or are electrically connected to, a respective word line of the monolithic three-dimensional NAND memory device;
the substrate comprises a silicon substrate;
the monolithic three-dimensional NAND memory device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;
at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;
the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and
the array of monolithic three-dimensional NAND strings comprises:
a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;
a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and
a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in the first device level and a second control gate electrode located in the second device level.

Assignees

• Sandisk Technologies Inc
• Sandisk Technologies Llc

Inventors

• Liu Jin
• Zhang Yanli
• Chowdhury Murshed
• Makala Raghuveer S
• Alsmeier Johann

Classifications

• H10W90/732

  between stacked chips · CPC title

• H01L27/11551

  Electricity · mapped topic

• H01L21/8221

  Electricity · mapped topic

• H01L29/66833

  Electricity · mapped topic

• H01L27/0688

  Electricity · mapped topic