Package structure having a plurality of conductive balls with narrow width for ball waist

Patent metadata

Field	Value
Publication number	US-10535593-B2
Application number	US-201916396767-A
Country	US
Kind code	B2
Filing date	Apr 29, 2019
Priority date	Jun 26, 2017
Publication date	Jan 14, 2020
Grant date	Jan 14, 2020

Abstract

A package structure including a circuit substrate, a semiconductor die, a redistribution layer, a plurality of conductive balls and a circuit substrate is provided. The redistribution layer is disposed on the semiconductor die, and being electrically connected to the semiconductor die. The plurality of conductive balls is disposed between the redistribution layer and the circuit substrate. The semiconductor die is electrically connected to the circuit substrate through the conductive balls. Each of the conductive balls has a ball foot with a first width D1, a ball head with a third width D3 and a ball waist with a second width D2 located between the ball foot and the ball head. The ball foot is connected to the redistribution layer, the ball head is connected to the circuit substrate, and the ball waist is the narrowest portion of each of the conductive balls.

First claim

What is claimed is:

1. A structure, comprising:
a first substrate having conductive pads;
a second substrate having conductive layers;
a plurality of conductive balls disposed in between the conductive pads of the first substrate and the conductive layers of the second substrate, the plurality of conductive balls is physically joined and in contact with the conductive pads and the conductive layers, and electrically connecting the conductive pads to the conductive layers, wherein each of the conductive balls has a calabash shape with curved sidewalls, and the curved sidewalls extend beyond a lateral dimension of the conductive pads of the first substrate.

2. The structure according to claim 1 , wherein the conductive balls having the calabash shape includes a ball head, a ball foot and a waist portion, the ball head is connected to the conductive pads, the ball foot is connected to the conductive layers and has the curved sidewalls, the waist portion is located between the ball head and the ball foot and joining the ball head to the ball foot.

3. The structure according to claim 2 , wherein the ball foot has a first width D 1 , the waist portion has a second width D 2 , the ball head has a third width D 3 , and the waist portion having the second width D 2 is the narrowest portion of the conductive balls.

4. The structure according to claim 3 , wherein each of the conductive balls satisfies the relationship of D 3 >D 1 >D 2 , and a ratio of D 1 :D 2 :D 3 is in a range from 1.1:1.0:1.5 to 1.2:1.1:1.25.

5. The structure according to claim 3 , wherein each of the conductive balls satisfies the relationship of D 1 >D 3 ≥D 2 , and a ratio of D 1 :D 2 :D 3 is in a range of 1.1:1.0:1.0 to 1.2:1.1:1.1.

6. The structure according to claim 1 , further comprising an upholding layer located on the second substrate and partially covering the plurality of conductive balls.

7. The structure according to claim 6 , wherein an air gap exists in between an upper surface of the upholding layer and a top surface of the first substrate, and portions of the conductive balls are exposed from the upholding layer and exposed to the air gap.

8. A structure, comprising:
a plurality of conductive balls, wherein each of the conductive balls has a first terminal having curved sidewalls, a second terminal having sidewalls, and a ball waist between the curved sidewalls of the first terminal and the sidewalls of the second terminal, and the ball waist is the narrowest portion of each of the conductive balls;
a package comprising dielectric layers and conductive layers, wherein the conductive layers is joined with the first terminals of the conductive balls, and the dielectric layers partially covers the curved sidewalls of the first terminals;
a circuit substrate having conductive pads joined with the second terminals of the conductive balls;
an upholding layer located on the dielectric layers of the package and partially covering the curved sidewalls of the first terminals, and an upper surface of the upholding layer is leveled with the ball waist.

9. The structure according to claim 8 , wherein the curved sidewalls of the first terminal extend beyond a lateral dimension of the conductive pads of the circuit substrate.

10. The structure according to claim 8 , wherein an air gap exists in between the upper surface of the upholding layer and a top surface of the circuit substrate, and the sidewalls of the second terminal are exposed from the upholding layer and exposed to the air gap.

11. The structure according to claim 8 , wherein a height of the upholding layer is about half of a height of the plurality of conductive balls.

12. The structure according to claim 8 , wherein the first terminal has a first width D 1 , the ball waist has a second width D 2 , and the second terminal has a third width D 3 , each of the conductive balls satisfies the relationship of D 3 >D 1 >D 2 , and a ratio of D 1 :D 2 :D 3 is in a range from 1.1:1.0:1.5 to 1.2:1.1:1.25.

13. The structure according to claim 8 , wherein the first terminal has a first width D 1 , the ball waist has a second width D 2 , and the second terminal has a third width D 3 , each of the conductive balls satisfies the relationship of D 1 >D 3 ≥D 2 , and a ratio of D 1 :D 2 :D 3 is in a range of 1.1:1.0:1.0 to 1.2:1.1:1.1.

14. The structure according to claim 8 , wherein the first terminal has a width D 1 that is the widest portion of the first terminal, a portion of the first terminal joined with the conductive layers is narrower than the width D 1 , and a portion of the first terminal joined with the second terminal at the ball waist is narrower than the width D 1 .

15. The structure according to claim 14 , wherein the second terminal has a width D 3 that is the widest portion of the second terminal, a portion of the second terminal joined with the conductive pads is narrower than the width D 3 , and a portion of the second terminal joined with the first terminal at the ball waist is narrower than the width D 3 .

16. A method of fabricating a package structure, comprising:
providing a package having conductive layers;
forming a plurality of first conductive portions on the conductive layers;
after forming the plurality of first conductive portions on the conductive layers, performing a partial melting process to partially melt the plurality of first conductive portions;
providing a circuit substrate and a plurality of second conductive portions on the circuit substrate;
mounting the package on the circuit substrate so that the plurality of second conductive portions is located in between the circuit substrate and the plurality of first conductive portions; and
joining the plurality of the second conductive portions with the plurality of the first conductive portions to form a plurality of conductive balls by performing a reflow process, wherein the circuit substrate is electrically connected to the package through the plurality of conductive balls.

17. The method according to claim 16 , further comprising forming an upholding layer after the partial melting process to partially cover the first conductive portions.

18. The method according to claim 16 , wherein a height of the first conductive portions and a height of the second conductive portions is reduced after forming the plurality of conductive balls by performing the reflow process.

19. The method according to claim 16 , wherein the partial melting process is performed at a same temperature range as the reflow process.

20. The method according to claim 16 , wherein joining the plurality of the second conductive portions with the plurality of the first conductive portions to form the plurality of conductive balls comprises forming ball waists of the plurality of the conductive balls at an interface where the plurality of the second conductive portions is joined with the plurality of the first conductive portions.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Pi-Lan
• Chen Chen-Shien
• Ku Chin-Yu
• Chen Hsu-Hsien
• Huang Wei-Chih
• Lin Chun-Ying
• Chou Li-Chieh

Classifications

• H10W74/117

  the substrate having spherical bumps for external connection · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/129

  forming a chip-scale package [CSP] · CPC title