Methods and Apparatus of Packaging with Interposers

Patent metadata

Field	Value
Publication number	US-2016204079-A1
Application number	US-201615078843-A
Country	US
Kind code	A1
Filing date	Mar 23, 2016
Priority date	Dec 13, 2012
Publication date	Jul 14, 2016
Grant date	—

Abstract

Methods and apparatus for forming a semiconductor device package on an interposer using a micro-bump layer are disclosed. The micro-bump layer may comprise micro-bumps and micro-bump lines, where a micro-bump is used as a vertical connection between a die and the interposer, and a micro-bump line is used as a horizontal connection for signal transmission between different dies above the interposer. The micro-bump lines may be formed at the same time as the formation of the micro-bumps with little or no additional cost.

First claim

What is claimed is:

1 . A device comprising:
an interposer comprising:
an insulator layer at a top surface of the interposer; and
a first contact pad over the insulator layer and electrically connected to a metal layer within the interposer;
a first die and a second die over the interposer, wherein the first die is disposed laterally adjacent the second die; a first conductive feature electrically connecting the first die to the second die, wherein the first conductive feature is disposed between the insulator layer and the first die, and wherein the insulator layer covers an entire bottom surface of the first conductive feature; and a second conductive feature electrically connecting the first die to the first contact pad.

2 . The device of claim 1 , wherein the first conductive feature and the second conductive feature are of a substantially similar height.

3 . The device of claim 1 , wherein the first conductive feature and a second conductive feature each comprise:
a copper layer over the insulating layer; and a solder layer over the copper layer.

4 . The device of claim 3 , wherein the first conductive feature and a second conductive feature each comprise a nickel layer between the copper layer and the solder layer.

5 . The device of claim 1 further comprising an underfill between the interposer and the first die, wherein the underfill is disposed around first conductive feature and the second conductive feature.

6 . The device of claim 1 , wherein the first conductive feature further comprises a first under bump metallurgy contacting a top surface of the insulating layer.

7 . The device of claim 1 , wherein the first conductive feature is electrically connected to a first solder ball disposed on a surface of the first die and a second solder ball disposed on a surface of the second die.

8 . The device of claim 1 , wherein the second conductive feature extends through an opening in the insulator layer to contact the metal layer in the interposer.

9 . A device comprising:
an interposer comprising:
a first metal line;
a second metal line adjacent the first metal line;
an insulating layer over the first metal line and the second metal line;
a first contact pad extending through the insulating layer and electrically connected to the first metal line and the second metal line; and
a second contact pad extending through the insulating layer;
a first conductive feature on the first contact pad; a second conductive feature on the second contact pad, wherein the second conductive feature is electrically connected to a first die; and an underfill between the first die and the interposer, wherein the underfill covers an entire top surface of the first conductive feature.

10 . The device of claim 9 further comprising a second die adjacent the first die and electrically connected to the interposer.

11 . The device of claim 9 , wherein the first conductive feature and the second conductive feature are formed of a same material.

12 . The device of claim 11 , wherein the first conductive feature and the second conductive feature each comprise a copper layer and a solder layer over the copper layer.

13 . The device of claim 9 , wherein the first contact pad extends through a first opening in the insulating layer and a second opening in the insulating layer, and wherein a portion of the insulating layer is disposed between the first opening and the second opening.

14 . The device of claim 13 , wherein a portion of the first contact pad covers the portion of the insulating layer between the first opening and the second opening.

15 . The device of claim 9 , wherein the first contact pad is in physical contact with the first metal line and the second metal line.

16 . A device comprising:
an interposer; a first conductive feature over the interposer; a first solder ball bonding the first conductive feature to a first die; and a second solder ball bonding the first conductive feature to a second die adjacent the first die, wherein the first conductive feature transmits electrical signals between the first die and the second die without transmitting the electrical signals through the interposer.

17 . The device of claim 16 further comprising an under bump metallurgy (UBM) on a top surface of the interposer, wherein the first conductive feature is disposed on the UBM.

18 . The device of claim 16 further comprising a second conductive feature adjacent the first conductive feature, wherein the second conductive feature electrically connects the first die to a metal line in the interposer.

19 . The device of claim 18 , wherein the first conductive feature and the second conductive feature each comprise:
a copper layer; a nickel layer; and a solder layer over the copper layer.

20 . The device of claim 19 , wherein the interposer comprises an insulating layer at a top surface, and wherein the insulating layer covers an entire bottom surface of the first conductive feature.

Assignees

• Taiwan Semiconductor Mfg

Inventors

• Lu Chung-Yu
• Hu Hsien-Pin
• Yen Hsiao-Tsung
• Liu Tzuan-Horng
• Huang Shih-Wen
• Hou Shang-Yun
• Jeng Shin-Puu

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/723

  between laterally-adjacent chips · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/07253

  changes in shapes · CPC title

• H10W72/07252

  changes in structures or sizes · CPC title