Programmable channel equalization for multi-level signaling

Patent metadata

Field	Value
Publication number	US-10530617-B2
Application number	US-201815885532-A
Country	US
Kind code	B2
Filing date	Jan 31, 2018
Priority date	Aug 7, 2017
Publication date	Jan 7, 2020
Grant date	Jan 7, 2020

Abstract

A memory interface may include a transmitter that generates multi-level signals. The transmitter may employ channel equalization to improve the quality and robustness of the multi-level signals. The channel equalization may be controlled independently from the drive strength of the multi-level signals. For example, a first control signal may control the de-emphasis or pre-emphasis applied to a multi-level signal and a second control signal may control the drive strength of the multi-level signal. The first control signal may control a channel equalization driver circuit and the second control signal may control a driver circuit.

First claim

What is claimed is:

1. An apparatus, comprising:
a driver circuit in electronic communication with a first control line, the driver circuit configured to modify its output current based at least in part on a first control signal received over the first control line, wherein the output current of the driver circuit is associated with a signal representing a bit in a symbol of a multi-level signal; and
a channel equalization driver circuit in electronic communication with a second control line different than the first control line, the channel equalization driver circuit comprising a plurality of sub-circuits each controlled by a second control signal received over the second control line, wherein the output current of the channel equalization driver circuit is associated with a delayed and inverted version of the signal representing the bit in the symbol of the multi-level signal.

2. The apparatus of claim 1 , wherein the first control signal comprises a first set of signals and the second control signal comprises a second set of signals different than the first set of signals.

3. The apparatus of claim 1 , further comprising:
a first pre-driver circuit configured to transfer the first control signal to the driver circuit; and
a second pre-driver circuit configured to and transfer the second control signal to the channel equalization driver circuit.

4. The apparatus of claim 1 , wherein the driver circuit comprises a plurality of sub-circuits and each sub-circuit is controlled by the first control signal.

5. The apparatus of claim 4 , wherein each sub-circuit is configured to modify the output current of the driver circuit by a pre-defined amount when activated.

6. The apparatus of claim 1 , wherein each sub-circuit is configured to modify the output current of the channel equalization driver circuit by a pre-defined amount when activated.

7. The apparatus of claim 1 , wherein the channel equalization driver circuit comprises a first plurality of sub-circuits and the driver circuit comprises a second plurality of sub-circuits different than the first plurality of sub-circuits.

8. A method, comprising:
receiving a first control signal at a driver circuit over a first control line;
receiving a second control signal different than the first control signal at a channel equalization driver circuit over a second control line different than the first control line;
receiving the second control signal at a second channel equalization driver circuit over the second control line, wherein the second control signal activates the channel equalization driver circuit and de-deactivates the second channel equalization driver circuit;
modifying an output current of the driver circuit based at least in part on the first control signal; and
modifying an output current of the channel equalization driver circuit based at least in part the second control signal.

9. The method of claim 8 , wherein the driver circuit comprises a plurality of sub-circuits and the first control signal activates at least one sub-circuit of the plurality of sub-circuits.

10. The method of claim 8 , wherein the channel equalization driver circuit comprises a plurality of sub-circuits and the second control signal activates at least one sub-circuit of the plurality of sub-circuits.

11. The method of claim 8 , further comprising:
combining a first output signal associated with the output current of the driver circuit and a second output signal associated with the output current of the channel equalization driver circuit; and
transferring the combined first and second output signals to a receiver circuit.

12. The method of claim 8 , further comprising:
receiving a data signal at the driver circuit; and
receiving a delayed and inverted version of the data signal at the channel equalization driver circuit, wherein modifying the output current of the driver circuit is based at least in part on modifying a strength of the data signal, and wherein modifying the output current of the channel equalization driver circuit is based at least in part on modifying a strength of the delayed and inverted version of the data signal.

13. The method of claim 8 , further comprising:
activating at least one sub-circuit of the driver circuit based at least in part on the first control signal, wherein modifying the output current of the driver circuit is based at least in part on activating the at least one sub-circuit of the driver circuit.

14. The method of claim 8 , further comprising:
activating at least one sub-circuit of the channel equalization driver circuit based at least in part on the second control signal, wherein modifying the output current of the channel equalization driver circuit is based at least in part on activating the at least one sub-circuit of the channel equalization driver circuit.

15. The method of claim 8 , wherein the channel equalization driver circuit comprises a de-emphasis driver circuit or a pre-emphasis driver circuit.

16. A method, comprising:
receiving a first control signal at a driver circuit over a first control line;
receiving a second control signal different than the first control signal at a channel equalization driver circuit over a second control line different than the first control line;
receiving the first control signal at a second driver circuit over the first control line, wherein the first control signal activates the driver circuit and de-deactivates the second driver circuit;
modifying an output current of the driver circuit based at least in part on the first control signal; and
modifying an output current of the channel equalization driver circuit based at least in part the second control signal.

17. An apparatus, comprising:
a driver circuit comprising a first input in electronic communication with an output of a first pre-driver circuit and a second input in electronic communication with a first control line, the driver circuit configured to modify a strength of a first output signal of the first pre-driver circuit based at least in part on a first control signal received over the first control line; and
a channel equalization driver circuit comprising a third input in electronic communication with an output of a second pre-driver circuit and a fourth input in electronic communication with a second control line, the channel equalization driver circuit configured to modify, based at least in part on a second control signal received over the second control line, a strength of a second output signal of the second pre-driver circuit by increasing or decreasing an output current of the channel equalization driver circuit.

18. The apparatus of claim 17 , wherein the driver circuit is configured to modify the strength of the first output signal by increasing an output current of the driver circuit or decreasing an output current of the driver circuit.

19. The apparatus of claim 17 , wherein the channel equalization driver circuit comprises a de-emphasis driver circuit or a pre-emphasis driver circuit.

Assignees

• Micron Technology Inc

Inventors

• Lin Feng

Classifications

• H04L25/0288 Primary

  the shape being matched to the transmission line (pre-equalisation per se H04L25/03343) · CPC title

• H04L25/03343

  Arrangements at the transmitter end · CPC title

• H04L25/03885 Primary

  adaptive · CPC title

• H04L2025/03363

  Multilevel (H04L2025/03369 takes precedence) · CPC title

• H04L2025/03777

  characterised by the signalling · CPC title