Data pattern generation for I/O testing of multilevel interfaces

Patent metadata

Field	Value
Publication number	US-9324454-B2
Application number	US-201314144432-A
Country	US
Kind code	B2
Filing date	Dec 30, 2013
Priority date	Dec 30, 2013
Publication date	Apr 26, 2016
Grant date	Apr 26, 2016

Abstract

One feature is a method of reading data from a plurality of pattern registers, generating a first output at a mapping register from the read data, generating a second output, different from the first output, at the mapping register from the read data, and generating a multi-level signal using the first and second outputs. In one embodiment, generating the first output is done by adding a first plurality of bits to a second plurality of bits, and generating the second output is done by adding the first plurality of bits to an inverse of the second plurality of bits.

First claim

What is claimed is:

1. A method of operating a device, comprising:
reading data from one or more pattern registers of the device via a built-in test circuit;
generating, via the built-in test circuit, a first output from a first mapping register using the read data;
generating, via the built-in test circuit, a second output, different from the first output, from the first mapping register or a second mapping register using the read data; and
generating a multi-level signal in the built-in test circuit using the first and second outputs.

2. The method of claim 1 , wherein reading data comprises:
reading a first plurality of bits from a first pattern register; and
reading a second plurality of bits from a second pattern register, and wherein generating the first and second outputs comprises:
generating the first output by adding the first plurality of bits to the second plurality of bits; and
generating the second output by adding the first plurality of bits to an inverse of the second plurality of bits.

3. The method of claim 1 , wherein the first output is generated using a first pattern register and the first mapping register, and the second output is generated using the first pattern register and the second mapping register.

4. The method of claim 1 , wherein the first output is generated using a first pattern register and the first mapping register, and the second output is generated using a second pattern register and the first mapping register.

5. The method of claim 1 , wherein the one or more pattern registers are within a memory circuit and coupled to output drivers for the memory circuit, and data patterns are stored in the one or more pattern registers.

6. The method of claim 5 , wherein the multi-level signal is inserted into data lines extending between a memory cell array and the plurality of output drivers for the memory circuit.

7. The method of claim 1 , wherein reading data comprises:
reading a first plurality of bits from a first pattern register; and
reading a second plurality of bits from a second pattern register.

8. The method of claim 7 , wherein generating the first output and second output comprises:
generating the first output by adding the first plurality of bits to the second plurality of bits;
shifting the second plurality of bits at least one place with a linear-feedback-shift-register to create a modified second plurality of bits; and
generating the second output by adding the first plurality of bits to the modified second plurality of bits.

9. The method of claim 7 , wherein the first pattern register is a read-only register and the first plurality of bits are pre-stored in the first pattern register.

10. The method of claim 1 , further comprising:
performing an input/output test operation using the first and second outputs.

11. The method of claim 10 , wherein the input/output (I/O) test operation serves to at least partially characterize a performance of output drivers using the multi-level signal.

12. The method of claim 1 , wherein the multi-level signal defines at least three current or voltage levels or states.

13. The method of claim 1 , wherein the generating a multi-level signal using the first and second outputs comprises:
generating the multi-level signal using the first and second outputs using pulse-amplitude modulation, such the generated multi-level signal defines:
a zero level when no output is received;
a first level when only the first output is received;
second level when only the second output is received; and
a third level when both the first and the second outputs are received, wherein the zero level, the first level, the second level, and the third level are all different voltage or current levels.

14. A device comprising:
a memory cell array;
a plurality of output drivers coupled to the memory cell array via a plurality of data lines; and
a built-in self-test circuit operationally coupled to the plurality of data lines, the built-in self-test circuit configured to:
read data from one or more pattern registers;
generate a first output from a first mapping register using the read data;
generate a second output, different from the first output, from the first mapping register or a second mapping register using the read data; and
generate a multi-level signal using the first and second outputs.

15. The device of claim 14 , wherein the built-in self-test circuit is further configured to:
read a first plurality of bits from a first pattern register; and
read a second plurality of bits from a second pattern register, and wherein generating the first and second outputs comprises:
generate the first output by adding the first plurality of bits to the second plurality of bits; and
generate the second output by adding the first plurality of bits to an inverse of the second plurality of bits.

16. The device of claim 14 , wherein the first output is generated using a first pattern register and the first mapping register, and the second output is generated using the first pattern register and the second mapping register.

17. The device of claim 14 , wherein the first output is generated using a first pattern register and the first mapping register, and the second output is generated using a second pattern register and the first mapping register.

18. The device of claim 14 , wherein the one or more pattern registers are within a memory circuit that also includes the memory cell array and the plurality of output drivers, the one or more pattern registers are couple to the output drivers and data patterns are stored in the one or more pattern registers.

19. The device of claim 18 , wherein the multi-level signal is inserted into data lines extending between the memory cell array and the plurality of output drivers.

20. The device of claim 14 , wherein reading data from one or more pattern registers comprises:
reading a first plurality of bits from a first pattern register; and
reading a second plurality of bits from a second pattern register.

21. The device of claim 14 , wherein the first pattern register is a read-only register and the first plurality of bits are pre-stored in the first pattern register.

22. The device of claim 14 , wherein the built-in self-test circuit is further configured to:
perform an input/output test operation using the first and second outputs.

23. The device of claim 22 , wherein the input/output (I/O) test operation serves to at least partially characterize a performance of the output drivers using the multi-level signal.

24. The device of claim 14 , wherein the multi-level signal defines at least three current or voltage levels or states.

25. The device of claim 14 , wherein the built-in self-test circuit is further configured to: generate the multi-level signal using the first and second outputs using pulse-amplitude modulation, such the generated multi-level signal defines:
a zero level when no output is received;
a first level when only the first output is received;
second level when only the second output is received; and
a third level when both the first and the second outputs are received, wherein the zero level, the first level, the second level, and the third level are all different voltage or current levels.

26. A memory circuit, comprising:
means for reading data from one or more pattern registers;
means for generating a first output from a first mapping

Assignees

• Qualcomm Inc

Inventors

• Hollis Timothy Mowry

Classifications

• G11C29/022

  in I/O circuitry · CPC title

• G06F11/263

  Generation of test inputs, e.g. test vectors, patterns or sequences {; with adaptation of the tested hardware for testability with external testers} · CPC title

• G11C2029/1206

  Location of test circuitry on chip or wafer · CPC title

• G11C29/36 Primary

  Data generation devices, e.g. data inverters · CPC title

• G11C2029/3602

  Pattern generator · CPC title