Apparatuses and methods for adding offset delays to signal lines of multi-level communication architectures

Patent metadata

Field	Value
Publication number	US-2016119169-A1
Application number	US-201414531558-A
Country	US
Kind code	A1
Filing date	Nov 3, 2014
Priority date	Oct 22, 2014
Publication date	Apr 28, 2016
Grant date	—

Abstract

Apparatuses and methods for adding offset delays to signal lines of multi-level communication architectures are disclosed herein. An example method may include comparing a current channel state of a channel of a multi-level communication bus with a next channel state of the channel. The example method may further include, based on the comparison, applying an offset delay to a control signal configured to control transition of a signal line of the channel from a value associated with the current channel state to a value associated with the next channel state. The example method may further include after application of the offset delay, driving the signal line to the value associated with the next channel state responsive to the control signal.

First claim

What is claimed is:

1 . An apparatus, comprising:
an output driver circuit configured to drive a channel based on a next channel state using a multi-level communication architecture, the output driver circuit configured to apply an offset delay to delay transition of a signal line of the channel to a value associated with the next channel state based on a comparison between the next channel state and a current channel state, the output driver circuit further configured to drive the signal line to the value associated with the next channel state.

2 . The apparatus of claim 1 , wherein the signal is a first signal and the offset delay is a first offset delay, wherein the output driver circuit is further configured to apply a second offset delay to delay transition of a second signal line of the channel to a value associated with the next channel state based on the comparison between the next channel state and the current channel state, wherein the first offset delay is different than the second offset delay.

3 . The apparatus of claim 1 , wherein the output driver circuit includes a delay line configured to apply the offset delay to the signal line of the channel based on the comparison between the next channel state and the current channel state.

4 . The apparatus of claim 3 , wherein the delay line includes a plurality of delay circuits, wherein the delay line is configured to select a delay circuit of the plurality of delay circuits based on the comparison between the next channel state and the current channel state.

5 . The apparatus of claim 1 , wherein the output driver circuit includes delay control logic configured to select the offset delay from a lookup table based on the comparison between the next channel state and the current channel state.

6 . The apparatus of claim 1 , wherein the output driver circuit includes driver control logic configured to provide a control signal having a value based on the next channel state, wherein the offset delay is applied the control signal, wherein the output driver circuit drives the value of the signal line based on the control signal after application of the offset delay.

7 . The apparatus of claim 6 , wherein the output driver circuit includes a driver configured to receive the control signal after application of the offset delay, wherein the driver is configured to drive the value on the signal line based on the control signal.

8 . An apparatus, comprising:
an output driver circuit configured to drive a signal line of a channel based on a channel state using a multi-level communication architecture, wherein, within a symbol period, the output driver circuit configured to apply an offset delay to a signal line, wherein the offset delay causes an output signal value determined from the signal line value to transition through an edge crossing at a predetermined transition time within the symbol period, the output driver circuit further configured to drive the signal line to a value associated with channel state after application of the offset delay.

9 . The apparatus of claim 8 , wherein the output driver circuit is configured to select the offset delay based on a comparison of the next channel state with a current channel state.

10 . The apparatus of claim 9 , wherein the output driver circuit configured to select the offset delay comprises selection of the offset delay from a lookup table based on the comparison of the next channel state with the current channel state.

11 . The apparatus of claim 8 , further comprising a receiver circuit configured to receive the signal and to provide the output signal having a value based on the value of the signal line.

12 . The apparatus of claim 11 , wherein the multi-level communication architecture is a differential architecture, and wherein the channel includes a plurality of signal lines, wherein the receiver circuit is configured to provide the output signal having a value that is based on a comparison of two signal lines of the plurality of signal lines.

13 . The apparatus of claim 8 , wherein the multi-level communication architecture includes the MIPI C-PHY architecture.

14 . The apparatus of claim 8 , wherein the multi-level communication architecture includes pulse-amplitude modulation.

15 . The apparatus of claim 8 , wherein the signal line is a single ended signal that is at least three signal lines.

16 . The apparatus of claim 8 , wherein the value of associated with the next channel state is one of three voltage values.

17 . A method, comprising:
comparing a current channel state of a channel of a multi-level communication bus with a next channel state of the channel; based on the comparison, applying an offset delay to a control signal configured to control a transition of a signal line of the channel from a value associated with the current channel state to a value associated with the next channel state; and after application of the offset delay, driving the signal line to the value associated with the next channel state responsive to the control signal.

18 . The method of claim 17 , further comprising selecting a delay circuit of a plurality of delay circuits based on the comparison, wherein the selected delay circuit is configured to apply the offset delay to the control signal.

19 . The method of claim 17 , wherein selecting the delay circuit of the plurality of delay circuits based on the comparison comprises activating a switch to select the delay circuit responsive to a delay control signal.

20 . The method of claim 19 , further comprising providing the control signal to the selected delay circuit having a value based on the next channel state.

21 . The method of claim 17 , further comprising latching the next channel state after driving the signal line to the valued associated with the next channel state.

22 . The method of claim 21 , wherein latching of the next channel state comprises determining an output signal value from the value of the signal line, wherein next channel state is determined and latched based on the output signal value.

23 . The method of claim 17 , wherein comparing the current channel state to the next channel state, applying the offset delay to the control signal, and driving the signal line to the value associated with the next channel state occur during a first symbol period, the method further comprising, during a second symbol period that follows the first symbol period:
comparing the next channel state to a following channel state associated with the second symbol period; based on the comparison between the next channel state and the following channel state, applying a second offset delay to the control signal configured to control a transition of the signal line from the value associated with the next channel state to a value associated with the following channel state.

24 . A method, comprising:
during a symbol period, applying an offset delay to a signal line to cause an output signal value determined from a value of the signal line to transition through an edge crossing at a predetermined transition time within the symbol period, wherein the value of the signal line is based on a next channel state; and after application of the offset delay, driving the signal line to the value associated with the next channel state.

25 . The method of claim 24 , further comprising selecting the offset delay based on a comparison of a current chann

Assignees

• Micron Technology Inc

Inventors

• Schober Bruce W

Classifications

• H04L27/0014 Primary

  Carrier regulation (of chaotic carriers H04L27/001; for multicarrier receivers H04L27/2657) · CPC title

• H04L25/061

  providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of DC offset (removal of DC offset in coupling arrangements H04L25/029, H04L25/0296) · CPC title

• H04L25/14 Primary

  Channel dividing arrangements {, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver} · CPC title

• H04L25/4917

  using multilevel codes · CPC title