Driver structure for chip-to-chip communications

Patent metadata

Field	Value
Publication number	US-2016180897-A1
Application number	US-201514973530-A
Country	US
Kind code	A1
Filing date	Dec 17, 2015
Priority date	Dec 17, 2014
Publication date	Jun 23, 2016
Grant date	—

Abstract

Apparatus for chip-to-chip communications may include a first driving unit and a second driving unit. The first driving unit may receive input data, generate a first output data based on the input data, and output the first output data. The second driving unit may receive the input data, generate a second output data with a pre-emphasis peak and output the second output data. The second output data may be generated by delaying and inverting the input data, and have a predetermined weight.

First claim

What is claimed is:

1 . An apparatus comprising:
a first driving unit suitable for receiving input data, generating a first output data based on the input data, and outputting the first output data; and a second driving unit suitable for receiving the input data, generating a second output data with a pre-emphasis peak, and outputting the second output data, wherein the second output data is generated by delaying and to inverting the input data, and wherein the second output data has a predetermined weight.

2 . The apparatus of claim 1 , wherein the predetermined weight is determined such that a peak of the first output data is greater than the pre-emphasis peak of the second output data.

3 . The apparatus of claim 1 , wherein the first driving unit comprises:
a first pre-driver suitable for receiving the input data, inverting the input data, and outputting the inverted input data; and a first voltage driver with pull-up and pull-down devices, the first voltage driver suitable for receiving the inverted input data from the pre-driver, and toggling the inverted input data to output the first output data.

4 . The apparatus of claim 3 , wherein the second driving unit comprises:
a delay cell suitable for delaying the input data; a second pre-driver suitable for receiving the delayed input data, and outputting the delayed input data; and a second voltage driver with pull-up and pull-down devices, the second voltage driver suitable for toggling the delayed input data, and outputting the second output data.

5 . The apparatus of claim 4 , wherein the pre-emphasis peak is determined based on impedances of the first voltage driver and the second voltage driver.

6 . The apparatus of claim 4 , wherein a width of the pre-emphasis peak is determined based on a delay value of the delay cell.

7 . The apparatus of claim 4 , wherein an effective impedance of the first voltage driver and the second voltage driver is matched to an impedance of a transmission line.

8 . The apparatus of claim 4 , wherein the delay cell receives and delays the input data based on a clock with a pulse width substantially identical to that of the input data.

9 . The apparatus of claim 8 , wherein the clock includes a half-rate clock of a double data rate (DDR) memory system.

10 . The apparatus of claim 8 , wherein the delay cell comprises:
a first flip-flop suitable for receiving the input data and outputting a first data based on the clock; a second flip-flop suitable for receiving the first data and outputting a second data based on an inversion of the clock; a third flip-flop suitable for receiving the input data and outputting a third data based on the inversion of the clock; a fourth flip-flop suitable for receiving the third data and outputting a fourth data based on the clock; a first selector suitable for receiving the first data and the third data and outputting one of the first data and the third data based on the clock; and a second selector suitable for receiving the second data and the fourth data and outputting one of the second data and the fourth data based on the clock.

11 . A system comprising:
a transmitting chip; a receiving chip; and a transmission line coupled between the transmitting chip and the receiving chip, wherein the transmitting chip comprises: a first driving unit suitable for receiving input data, generating a first output data based on the input data, and outputting the first output data to the transmission line; and a second driving unit suitable for receiving the input data, generating a second output data with pre-emphasis peak, and outputting the second output data to the transmission line, wherein the second output data is generated by delaying and inverting the input data, and wherein the second output data has a predetermined weight.

12 . The system of claim 11 , wherein the predetermined weight is determined such that a peak of the first output data is greater than the pre-emphasis peak of the second output data.

13 . The system of claim 11 , wherein the first driving unit comprises:
a first pre-driver suitable for receiving the input data, inverting the input data, and outputting the inverted input data; and a first voltage driver with pull-up and pull-down devices, the first voltage driver suitable for receiving the inverted input data from the pre-driver, and toggling the inverted input data to output the first output data.

14 . The system of claim 13 , wherein the second driving unit comprises:
a delay cell suitable for delaying the input data; a second pre-driver suitable for receiving the delayed input data and outputting the delayed input data; and a second voltage driver with pull-up and pull-down devices, the second voltage driver suitable for toggling the delayed input data and outputting the second output data.

15 . The system of claim 14 , wherein the pre-emphasis peak is determined based on impedances of the first voltage driver and the second voltage driver.

16 . The system of claim 14 , wherein a width of the pre-emphasis peak determined based on a delay value of the delay cell.

17 . The system of claim 14 , wherein an effective impedance of the first voltage driver and the second voltage driver is matched to an impedance of a transmission line.

18 . The system of claim 14 , wherein the delay cell receives and delays the input data based on a clock with a pulse width substantially identical to that of the input data.

19 . The system of claim 18 , wherein the clock includes a half-rate clock of a double data rate (DDR) memory system.

20 . The system of claim 18 , wherein the delay cell comprises:
a first flip-flop suitable for receiving the input data and outputting a first data based on the clock; a second flip-flop suitable for receiving the first data and outputting a second data based on an inversion of the clock; a third flip-flop suitable for receiving the input data and outputting a third data based on the inversion of the clock; a fourth flip-flop suitable for receiving the third data and outputting a fourth data based on the clock; a first selector suitable for receiving the first data and the third data and outputting one of the first data and the third data based on the clock; and a second selector suitable for receiving the second data and the fourth data and outputting one of the second data and the fourth data based on the clock.

Assignees

• Sk Hynix Memory Solutions Inc

Inventors

• Shen Chun-Ju
• Chern Jenn-Gang
• Cheng Zichuan
• You Huei-Ching

Classifications

• G11C7/1057

  Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• G11C7/106 Primary

  Data output latches · CPC title

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G11C7/1048 Primary

  Data bus control circuits, e.g. precharging, presetting, equalising · CPC title