Semiconductor device and method for driving semiconductor device

Patent metadata

Field	Value
Publication number	US-10529413-B2
Application number	US-201816103157-A
Country	US
Kind code	B2
Filing date	Aug 14, 2018
Priority date	May 26, 2015
Publication date	Jan 7, 2020
Grant date	Jan 7, 2020

Abstract

The semiconductor device includes a first memory cell, and a second memory cell thereover. The first memory cell includes first and second transistors, and a first capacitor. The second memory cell includes third and fourth transistors, and a second capacitor. A gate of the first transistor is electrically connected to one of a source and a drain of the second transistor and the first capacitor. A gate of the third transistor is electrically connected to one of a source and a drain of the fourth transistor and the second capacitor. One of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor. The second and fourth transistors include an oxide semiconductor. A channel length direction of the first and third transistors is substantially perpendicular to a channel length direction of the second and fourth transistors.

First claim

What is claimed is:

1. A semiconductor device comprising:
a plurality of memory cell arrays arranged in a first direction;
a plurality of first wirings; and
a plurality of second wirings,
wherein the plurality of first wirings and the plurality of second wirings extend in a second direction substantially perpendicular to the first direction,
wherein each of the memory cell arrays includes a plurality of memory cell strings arranged in the second direction,
wherein the plurality of memory cell strings extend in a third direction substantially perpendicular to the first direction and the second direction,
wherein each of the memory cells string includes a plurality of memory cells and third to fifth wirings extending in the third direction,
wherein each of the memory cells includes a first transistor, a second transistor, and a capacitor,
wherein a channel length direction of the first transistor is substantially parallel to the third direction,
wherein the second transistor includes an oxide semiconductor,
wherein a gate of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein the one of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor,
wherein, in one of the plurality of memory cell strings,
one of a source and a drain of the first transistor of one of the plurality of memory cells is electrically connected to the other of the source and the drain of the first transistor of another one of the plurality of memory cells,
the one of the source and the drain of the first transistor of the memory cell at one end of the memory cell string is electrically connected to the third wiring,
the other of the source and the drain of the first transistor of the memory cell at the other end of the memory cell string is electrically connected to the fourth wiring, and
the other of the source and the drain of the second transistor of each of the plurality of memory cells is electrically connected to the fifth wiring, and

wherein, in one of the plurality of memory cell arrays,
the other electrode of the capacitor of each of the memory cells in a same row is electrically connected to one of the plurality of first wirings, and
a gate of the second transistor of each of the memory cells in a same row is electrically connected to one of the plurality of second wirings.

2. A method for driving the semiconductor device according to claim 1 ,
wherein, in a writing operation,
one of the plurality of memory cell arrays is selected,
the second transistor is turned on via one of the plurality of second wirings,
a writing potential is supplied to the plurality of fifth wirings, and
the second transistor is turned off via one of the plurality of second wirings to hold data corresponding to the writing potential, and

wherein, in a reading operation,
one of the plurality of memory cell arrays is selected,
a first potential is supplied to the other electrode of the capacitor via one of the plurality of first wirings,

a second potential different from the first potential is supplied to the other electrode of the capacitor via the first wiring in a row different from a row of the one of the plurality of first wirings so that the first transistor is turned on, and
a reading potential is supplied to the third wiring and the data is read from a change in the reading potential.

3. A semiconductor device comprising:
a plurality of memory cell arrays arranged in a first direction;
a plurality of selection transistor cells arranged in the first direction;
a plurality of first wirings; and
a plurality of second wirings,
wherein the plurality of first wirings and the plurality of second wirings extend in a second direction substantially perpendicular to the first direction,
wherein each of the memory cell arrays includes a plurality of memory cell strings arranged in the second direction,
wherein the plurality of memory cell strings extend in a third direction substantially perpendicular to the first direction and the second direction,
wherein each of the memory cells string includes a plurality of memory cells and third and fourth wirings extending in the third direction,
wherein each of the memory cells includes a first transistor, a second transistor, and a capacitor,
wherein a channel length direction of the first transistor is substantially parallel to the third direction,
wherein the second transistor includes an oxide semiconductor,
wherein a gate of the first transistor is electrically connected to one of a source and a drain of the second transistor,
wherein the one of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor,
wherein each of the selection transistor cells includes a third transistor and a fourth transistor,
wherein, in one of the plurality of memory cell strings,
one of a source and a drain of the first transistor of one of the plurality of memory cells is electrically connected to the other of the source and the drain of the first transistor of another one of the plurality of memory cells,
the one of the source and the drain of the first transistor of the memory cell at one end of the memory cell string is electrically connected to the third wiring, and
the other of the source and the drain of the second transistor of each of the plurality of memory cells is electrically connected to the fourth wiring, and

wherein, in one of the plurality of selection transistor cells,
one of a source and a drain of the third transistor of one of the plurality of selection transistor cells is electrically connected to the other of the source and the drain of the first transistor of the memory cell at the other end of the memory cell string of the one of the plurality of memory cell strings,
the other of the source and the drain of the third transistor of one of the plurality of selection transistor cells is electrically connected to a fifth wiring,
one of a source and a drain of the fourth transistor of one of the plurality of selection transistor cells is electrically connected to the fourth wiring of one of the plurality of memory cell strings, and
the other of the source and the drain of the fourth transistor of one of the plurality of selection transistor cells is electrically connected to a sixth wiring,

wherein, in one of the plurality of memory cell arrays,
the other electrode of the capacitor of each of the memory cells in a same row is electrically connected to one of the plurality of first wirings, and
a gate of the second transistor of each of the memory cells in a same row is electrically connected to one of the plurality of second wirings.

4. A method for driving the semiconductor device according to claim 3 ,
wherein, in a writing operation,
one of the plurality of memory cell arrays is selected,
the second transistor is turned on via one of the plurality of second wirings,
a writing potential is supplied to the plurality of fifth wirings, and
the second transistor is turned off via one of the plurality of second wirings to hold data corresponding to the writing potential, and

wherein, in a reading operation,
one of the plurality of memory cell arrays is selected,
a first potential is supplied to the other electrode of the capacitor via one of the plurality of first wirings,
a second potential different from the first potential is supplied to the other electrode of the capacitor via the first wiring in a row different from a row of the one of the plurality of first wirings so that the first transistor is turned on, and
a reading potential is supplied to the third wiring and the data is read from a change in the reading potential.

5. The semiconductor device accord

Assignees

• Semiconductor Energy Lab

Inventors

• Atsumi Tomoaki
• Sugao Junpei

Classifications

• G11C11/401

  forming cells needing refreshing or charge regeneration, i.e. dynamic cells · CPC title

• G11C11/4096

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C11/4097

  Bit-line organisation, e.g. bit-line layout, folded bit lines · CPC title

• G11C11/4094 Primary

  Bit-line management or control circuits · CPC title

• H01L27/1251

  Electricity · mapped topic