Semiconductor device comprising transistor including oxide semiconductor

Patent metadata

Field	Value
Publication number	US-9685447-B2
Application number	US-201615175190-A
Country	US
Kind code	B2
Filing date	Jun 7, 2016
Priority date	Oct 30, 2009
Publication date	Jun 20, 2017
Grant date	Jun 20, 2017

Abstract

An object is to provide a semiconductor device with a novel structure. The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is provided in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a first wiring, a second wiring, and a plurality of storage elements connected in parallel between the first wiring and the second wiring,
wherein one of the plurality of storage elements includes:
a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and
a second transistor having a second gate electrode, a second source electrode, and a second drain electrode,

wherein the first transistor includes a first channel region provided in a substrate including a semiconductor material,
wherein the second transistor includes an oxide semiconductor layer including a second channel region,
wherein the first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other,
wherein the first wiring and the first source electrode are electrically connected to each other, and
wherein the second wiring and the first drain electrode are electrically connected to each other.

2. The semiconductor device according to claim 1 , wherein the first transistor includes impurity regions provided so as to sandwich the channel region, a first gate insulating layer over the channel region, the first gate electrode over the first gate insulating layer, and the first source electrode and the first drain electrode electrically connected to the impurity regions.

3. The semiconductor device according to claim 1 , wherein the second transistor includes the second gate electrode over the substrate including the semiconductor material, a second gate insulating layer over the second gate electrode, the oxide semiconductor layer over the second gate insulating layer, and the second source electrode and the second drain electrode electrically connected to the oxide semiconductor layer.

4. The semiconductor device according to claim 1 , wherein the substrate including the semiconductor material is one of a single crystal semiconductor substrate and an SOI substrate.

5. The semiconductor device according to claim 1 , wherein the semiconductor material is silicon.

6. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer comprises Indium.

7. The semiconductor device according to claim 1 , wherein concentration of hydrogen in the oxide semiconductor layer is 5×10 19 /cm 3 or less.

8. The semiconductor device according to claim 1 , wherein an off-state current of the second transistor is 1×10 −13 A or less.

9. The semiconductor device according to claim 1 , further comprising an insulating layer over the first transistor,
wherein the second transistor is provided over the insulating layer.

10. A semiconductor device comprising:
a first wiring, a second wiring, a third wiring, and a fourth wiring, and a plurality of storage elements connected in parallel between the first wiring and the second wiring,
wherein one of the plurality of storage elements includes:
a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and

a second transistor having a second gate electrode, a second source electrode, and a second drain electrode,
wherein the first transistor includes a first channel region provided in a substrate including a semiconductor material,
wherein the second transistor includes an oxide semiconductor layer including a second channel region,
wherein the first gate electrode and one of the second source electrode and the second drain electrode are electrically connected to each other,
wherein the first wiring and the first source electrode are electrically connected to each other,
wherein the second wiring and the first drain electrode are electrically connected to each other,
wherein the third wiring and the other of the second source electrode and the second drain electrode are electrically connected to each other, and
wherein the fourth wiring and the second gate electrode are electrically connected to each other.

11. The semiconductor device according to claim 10 , wherein the first transistor includes impurity regions provided so as to sandwich the channel region, a first gate insulating layer over the channel region, the first gate electrode over the first gate insulating layer, and the first source electrode and the first drain electrode electrically connected to the impurity regions.

12. The semiconductor device according to claim 10 , wherein the second transistor includes the second gate electrode over the substrate including the semiconductor material, a second gate insulating layer over the second gate electrode, the oxide semiconductor layer over the second gate insulating layer, and the second source electrode and the second drain electrode electrically connected to the oxide semiconductor layer.

13. The semiconductor device according to claim 10 , wherein the substrate including the semiconductor material is one of a single crystal semiconductor substrate and an SOI substrate.

14. The semiconductor device according to claim 10 , wherein the semiconductor material is silicon.

15. The semiconductor device according to claim 10 , wherein the oxide semiconductor layer comprises Indium.

16. The semiconductor device according to claim 10 , wherein concentration of hydrogen in the oxide semiconductor layer is 5×10 19 /cm 3 or less.

17. The semiconductor device according to claim 10 , wherein an off-state current of the second transistor is 1×10 −13 A or less.

18. The semiconductor device according to claim 10 , further comprising an insulating layer over the first transistor,
wherein the second transistor is provided over the insulating layer.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Koyama Jun
• Kato Kiyoshi

Classifications

• G11C2211/4016

  Memory devices with silicon-on-insulator cells · CPC title

• G11C16/0433

  comprising cells containing a single floating gate transistor and one or more separate select transistors · CPC title

• H01L29/247

  Electricity · mapped topic

• H01L27/105

  Electricity · mapped topic

• G11C11/405 Primary

  with three charge-transfer gates, e.g. MOS transistors, per cell · CPC title