Non-volatile semiconductor storage device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9356042-B2
Application number	US-201514668270-A
Country	US
Kind code	B2
Filing date	Mar 25, 2015
Priority date	Dec 11, 2007
Publication date	May 31, 2016
Grant date	May 31, 2016

Abstract

A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.

First claim

The invention claimed is:

1. A semiconductor device comprising;
a substrate;
a first columnar portion extending in a first direction crossing to a surface of the substrate;
a second columnar portion extending in the first direction;
a first electrode layer surrounding at least a part of the first columnar portion; and
a contacting layer extending in a second direction crossing to the first direction above the substrate, the contacting layer being connected to a lower end of the first columnar portion and being connected to a lower end of the second columnar portion.

2. The semiconductor device according to claim 1 , further comprising:
an insulation layer disposed above the substrate, wherein
the contacting layer is disposed above the insulation layer.

3. The semiconductor device according to claim 1 , wherein
the first columnar portion is a part of a first memory transistor, and
the second columnar portion is a part of a second memory transistor.

4. The semiconductor device according to claim 3 , wherein the first electrode layer is a part of the first memory transistor.

5. The semiconductor device according to claim 3 , further comprising:
a memory portion provided between the first electrode layer and the first columnar portion.

6. The semiconductor device according to claim 1 , wherein the first columnar portion is a part of a first select transistor.

7. The semiconductor device according to claim 6 , wherein the second columnar portion is a part of a second select transistor.

8. The semiconductor device according to claim 7 , wherein a gate electrode layer of the first select transistor is separated from a gate electrode layer of the second select transistor.

9. The semiconductor device according to claim 1 , wherein the first columnar portion and the second columnar portion comprise semiconductor material.

10. The semiconductor device according to claim 1 , further comprising:
a gate electrode layer extending in a plane parallel to the surface of the substrate, the gate electrode layer being disposed on an upper surface of the contacting layer.

11. The semiconductor device according to claim 1 , further comprising:
a gate electrode layer being disposed to a side surface of the contacting layer.

12. The semiconductor device according to claim 1 , wherein the first columnar portion has an upper end, the first columnar portion having a maximum width at a middle level between the upper end and the lower end.

13. The semiconductor device according to claim 1 , wherein the contacting layer overlaps the lower end of the first columnar portion and the lower end of the second columnar portion in the second direction, an edge of the contacting layer being separated from an edge of the first columnar portion in a third direction crossing the second direction.

14. The semiconductor device according to claim 1 , wherein the first columnar portion has a first portion extending in the first direction, a second portion extending in the first direction, and a third portion extending in a fourth direction crossing the first direction.

15. The semiconductor device according to claim 14 , wherein
the third portion is connected to a lower end of the first portion and an upper end of the second portion, and
a lower end of the second portion is connected to the contacting layer.

16. The semiconductor device according to claim 1 , wherein the contacting layer comprises semiconductor material.

Assignees

• Toshiba Kk

Inventors

• Fukuzumi Yoshiaki
• Katsumata Ryota
• Kidoh Masaru
• Kito Masaru
• Tanaka Hiroyasu
• Komori Yosuke
• Ishiduki Megumi
• Aochi Hideaki

Classifications

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• H10D64/685

  being perpendicular to the channel plane · CPC title

• H01L29/513

  Electricity · mapped topic

• H01L27/11573

  Electricity · mapped topic

• H01L27/11556

  Electricity · mapped topic