Methods, apparatus and system for stringer defect reduction in a trench cut region of a finFET device

Patent metadata

Field	Value
Publication number	US-10522639-B2
Application number	US-201916458056-A
Country	US
Kind code	B2
Filing date	Jun 29, 2019
Priority date	Sep 26, 2017
Publication date	Dec 31, 2019
Grant date	Dec 31, 2019

Abstract

At least one method, apparatus and system disclosed herein involves forming trench in a gate region, wherein the trench having an oxide layer to a height to reduce or prevent process residue. A plurality of fins are formed on a semiconductor substrate. Over a first portion of the fins, an epitaxial (EPI) feature at a top portion of each fin of the first portion. Over a second portion of the fins, a gate region is formed. In a portion of the gate region, a trench is formed. A first oxide layer at a bottom region of the trench is formed. Prior to performing an amorphous-silicon (a-Si) deposition, a flowable oxide material is deposited into the trench for forming a second oxide layer. The second oxide layer comprises the flowable oxide and the first oxide layer. The second oxide layer has a first height.

First claim

What is claimed is:

1. A finFET device, comprising:
a plurality of fins on a substrate;
an epitaxial (EPI) region formed at a top portion of each fin of a first portion of the fins;
a gate region formed on a second portion of the fins;
a trench formed in a portion of the gate region, the trench comprising an oxide layer having a first height, wherein the first height is from the bottom of the trench up to a bottom portion of the EPI features, wherein the oxide layer is capable of substantially preventing a buildup of residue from a process step;
a plurality of spacers on the walls of the trench, wherein a lower portion of the space between the spacers is filled with the oxide layer; and
a low-k layer above the oxide layer in the trench and the gate region, wherein an upper portion of the space between the spacers is filled with the low-k layer, and the upper portion has a larger height than the lower portion.

2. The finFET device of claim 1 , further comprising a plurality of low-k spacers each adjacent the fins in the first portion of fins, wherein an upper portion of the oxide layer is capable of reducing a current leakage flow through the low-k liners.

3. The finFET device of claim 1 , wherein the upper portion of the oxide layer is formed from flowable oxide.

4. The finFET device of claim 1 , wherein the trench is an shallow isolation trench (STI) trench comprising:
a liner set comprising:
a SiN liner, and
an oxide liner adjacent the SiN liner; and wherein:
the plurality of spacers are low-k spacers adjacent the SiN liner;
wherein the oxide liner contacts the bottom portion of the trench up to the first height between the liner set;
and

the low-k layer is formed above the oxide liner between the liner set and between a first portion of the gate region and a second portion of the gate region.

5. The finFET device of claim 2 , further comprising a metal formation at least partially above the EPI formations and at least partially above the oxide layer.

6. A finFET device, comprising:
a plurality of fins on a semiconductor substrate;
an epitaxial (EPI) region formed at a top portion of each fin of a first portion of the fins;
a gate region formed on a second portion of the fins;
a trench formed in a portion of the gate region, the trench comprising an oxide layer having a first height, wherein the first height is from the bottom of the trench up to a bottom portion of the EPI features, wherein the oxide layer is capable of substantially preventing a buildup of residue from a process step;
an amorphous silicon (a-Si) layer disposed above the EPI region;
a plurality of spacers on the walls of the trench, wherein a lower portion of the space between the spacers is filled with the oxide layer; and
a low-k layer above the oxide layer in the trench and the gate region, wherein an upper portion of the space between the spacers is filled with the low-k layer, and the upper portion has a larger height than the lower portion.

7. The finFET device of claim 6 , further comprising a plurality of low-k spacers each adjacent the fins in the first portion of fins, wherein an upper portion of the oxide layer is capable of reducing a current leakage flow through the low-k liners.

8. The finFET device of claim 6 , wherein the upper portion of the oxide layer is formed from flowable oxide.

9. The finFET device of claim 6 , wherein the trench is an shallow isolation trench (STI) trench comprising:
a liner set comprising:
a SiN liner, and
an oxide liner adjacent the SiN liner; and wherein
the plurality of spacers are low-k spacer spacers adjacent the SiN liner;
wherein the oxide liner contacts the bottom portion of the trench up to the first height between the liner set; and
the low-k layer is formed above the oxide liner between the liner set and between a first portion of the gate region and a second portion of the gate region.

10. The finFET device of claim 7 , further comprising a metal formation at least partially above the EPI formations and at least partially above the oxide layer.

11. A finFET device, comprising:
a first gate region and a second gate region each positioned on fins;
an oxide stack positioned between the first gate region and the second gate region, the oxide stack comprising an oxide liner up to a first height, an oxide layer up to the first height, and a flowable oxide layer up to a second height about the first height; and
a plurality of spacers extending from the first height up to essentially a top of the first gate region and the second gate region, wherein a bottom of each spacers is in physical contact with a top of the oxide layer.

12. The FinFET device of claim 11 , further comprising:
a low-k layer formed above the flowable oxide layer and between the plurality of spacers.

Assignees

• Globalfoundries Inc

Inventors

• Zang Hui
• Jaeger Daniel
• Huang Haigou
• Basker Veeraraghavan
• Nassar Christopher
• Gao Jinsheng
• Aquilino Michael

Classifications

• H10P52/403

  of conductive or resistive materials · CPC title

• H10P32/1414

  the applied layer being silicon, silicide or SIPOS, e.g. polysilicon or porous silicon · CPC title

• H10P32/171

  being group IV material · CPC title

• H10P14/2923

  being conductive materials, e.g. metallic silicides · CPC title

• H10D64/0131

  the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation · CPC title