Opposite polarity borderless replacement metal contact scheme

Patent metadata

Field	Value
Publication number	US-9390979-B2
Application number	US-201414482529-A
Country	US
Kind code	B2
Filing date	Sep 10, 2014
Priority date	Sep 10, 2014
Publication date	Jul 12, 2016
Grant date	Jul 12, 2016

Abstract

An improved semiconductor structure and methods of fabrication that provide improved transistor contacts in a semiconductor structure are provided. A set of masks is formed over a portion of the semiconductor structure. Each mask in this set of masks covers at least one source/drain (s/d) contact location. An oxide layer is removed from remainder portions of the semiconductor structure that are not covered by the set of masks. Then an opposite-mask fill layer is formed in the remainder portions from which the oxide layer was removed. The oxide layer is then removed from the remainder of the semiconductor structure, i.e., the portion previously covered by the set of masks and contacts are formed to the at least s/d contact location in the recesses formed by the removal of the remainder of the oxide layer.

First claim

What is claimed is:

1. A method of forming a set of contacts in a semiconductor structure comprising:
forming a set of masks over a portion of the semiconductor structure, wherein each mask in the set of masks covers at least one source/drain (s/d) contact location;
removing a oxide layer from remainder portions of the semiconductor structure that are not covered by the set of masks;
removing the set of masks from the entire semiconductor structure;
forming an opposite-mask fill layer in the remainder portions of the semiconductor structure;
removing the oxide layer from the portion of the semiconductor structure previously covered by the set of masks; and
depositing a metal contact layer that forms a contact to the at least one s/d contact location in the portion of the semiconductor structure previously covered by the set of masks.

2. The method of claim 1 , wherein the set of masks comprises a block mask.

3. The method of claim 2 ,
wherein the block mask comprises a softmask, and
wherein the softmask comprises an SiC layer, an SiON layer, a TEOS memorization layer, a BARC layer, and a photoresist layer.

4. The method of claim 1 , wherein the set of masks comprises a separate lithography stack over each s/d contact location.

5. The method of claim 1 , further comprising:
forming, prior to the forming of the set of masks, the oxide layer covering the semiconductor structure;
forming a nitride layer over the oxide layer;
removing the nitride layer from all areas of the semiconductor structure not covered by the set of masks;
and
performing an etch selective to nitride to perform the removing of the oxide layer in the remainder portions of the semiconductor structure not covered by the nitride layer.

6. The method of claim 5 , further comprising:
performing the forming of the opposite-mask fill layer by depositing a silicon oxycarbide dielectric in the remainder portions of the semiconductor structure;
removing the nitride layer from the portion of the semiconductor structure previously covered by the set of masks;
removing a nitride liner layer from over the s/d contact location prior to the depositing of the metal contact layer; and
wherein performing the etch selective to nitride comprises performing a strip that is selective to the silicon oxycarbide dielectric to perform the removing of the oxide layer from the portion of the semiconductor structure previously covered by the set of masks.

7. The method of claim 6 , further comprising:
forming, prior to the forming of the oxide layer, a set of gate capping regions covering a set of gates in the semiconductor structure,
wherein the set of gate capping regions comprise a nitride, and
wherein the set of gate capping regions protect a material forming the set of gates during the removing of the oxide layer from the remainder portions of the semiconductor structure that are not covered by the set of masks and during the removing of the oxide layer from the portion of the semiconductor structure previously covered by the set of masks.

8. The method of claim 7 , wherein the set of gates comprise replacement metal gates (RMG) in a RMG transistor.

9. A method of forming a semiconductor device comprising:
forming a set of source-drain (s/d) regions and a set of replacement metal gates on a substrate;
forming a set of gate capping regions over the set of replacement metal gates;
forming an oxide layer over the semiconductor device;
forming a set of masks over a portion of the semiconductor device, wherein each mask in the set of masks covers at least one source/drain (s/d) contact location;
removing the oxide layer from remainder portions of the semiconductor device that are not covered by the set of masks;
removing the set of masks from the entire semiconductor structure;
forming a silicon oxycarbide dielectric layer in the remainder portions of the semiconductor device;
removing the oxide layer from the portion of the semiconductor device previously covered by the set of masks; and
depositing a metal contact layer that forms a contact to the at least one s/d contact location in the portion of the semiconductor device previously covered by the set of masks.

10. The method of claim 9 ,
wherein the set of masks comprises a block mask,
wherein the block mask comprises a softmask, and
wherein the softmask comprises an SiC layer, an SiON layer, a TEOS memorization layer, a BARC layer, and a photoresist layer.

11. The method of claim 9 , wherein the set of masks comprises a separate lithography stack over each s/d contact location.

12. The method of claim 9 , further comprising:
forming, prior to the forming of the set of masks, a nitride layer covering the oxide layer;
removing the nitride layer from all areas of the semiconductor structure not covered by the set of masks;
and
performing an etch selective to nitride to perform the removing of the oxide layer in the remainder portions of the semiconductor structure not covered by the nitride layer.

13. The method of claim 12 , further comprising:
removing the nitride layer from the portion of the semiconductor structure previously covered by the set of masks;
removing a nitride liner layer from over the s/d contact location prior to the depositing of the metal contact layer; and
wherein performing the etch selective to nitride comprises performing a strip that is selective to the silicon oxycarbide dielectric to perform the removing of the oxide layer from the portion of the semiconductor structure previously covered by the set of masks.

14. The method of claim 13 ,
wherein the set of gate capping regions comprise a nitride, and
wherein the set of gate capping regions protect a material forming the set of gates during the removing of the oxide layer from the remainder portions of the semiconductor structure that are not covered by the set of masks and during the removing of the oxide layer from the portion of the semiconductor structure previously covered by the set of masks.

Assignees

• Globalfoundries Inc

Inventors

• Wei Andy Chih-Hung
• Bouche Guillaume
• Cao Huy M
• Wan Jing

Classifications

• H10P50/695

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title

• H10P50/694

  characterised by their behaviour during the process, e.g. soluble masks or redeposited masks · CPC title

• H10P50/692

  characterised by their composition, e.g. multilayer masks or materials · CPC title

• H10P50/283

  by chemical means · CPC title

• H10P50/73

  using masks for insulating materials · CPC title