Three-dimensional semiconductor devices with inclined gate electrodes

Patent metadata

Field	Value
Publication number	US-10515979-B2
Application number	US-201715692281-A
Country	US
Kind code	B2
Filing date	Aug 31, 2017
Priority date	Feb 3, 2017
Publication date	Dec 24, 2019
Grant date	Dec 24, 2019

Abstract

A three-dimensional semiconductor device includes a substrate including a cell array region and a contact region, a stack structure including gate electrodes sequentially stacked on the substrate, vertical structures penetrating the stack structure, and cell contact plugs connected to end portions of the gate electrodes in the contact region. Upper surfaces of the end portions of the gate electrodes have an acute angle with respect to an upper surface of the substrate in the cell array region.

First claim

What is claimed is:

1. A three-dimensional semiconductor memory device comprising:
a substrate comprising a cell array region and a contact region;
a stack structure comprising gate electrodes sequentially stacked on the substrate;
vertical structures penetrating the stack structure; and
cell contact plugs in contact with upper surfaces of end portions of the gate electrodes in the contact region,
wherein the upper surfaces of the end portions of the gate electrodes in the contact region have a first acute angle with respect to an upper surface of the substrate in the cell array region,
wherein a lower surface of each of the cell contact plugs is located at a level higher than that of a lower surface of each of the gate electrodes connected thereto.

2. The three-dimensional semiconductor memory device of claim 1 , wherein the gate electrodes comprise an uppermost gate electrode,
wherein the stack structure further comprises first insulating patterns between the gate electrodes and a second insulating pattern on the uppermost gate electrode, and
wherein an upper surface of the second insulating pattern is positioned at a higher level than the upper surfaces of the end portions of the gate electrodes with respect to the upper surface of the substrate.

3. The three-dimensional semiconductor memory device of claim 1 , wherein the substrate further comprises a peripheral circuit region adjacent to the contact region, and
wherein an uppermost portion of the upper surfaces of the end portions of the gate electrodes are at a higher level than the upper surface of the substrate in the peripheral circuit region.

4. The three-dimensional semiconductor memory device of claim 1 , wherein the substrate further comprises a peripheral circuit region, the contact region disposed between the cell array region and the peripheral circuit region,
wherein the upper surface of the substrate in the cell array region is positioned at a lower level than the upper surface of the substrate in the peripheral circuit region, and
wherein the upper surface of the substrate in the contact region has a second acute angle with respect to the upper surface of the substrate in the cell array region and extends from the upper surface of the substrate in the peripheral circuit region to the upper surface of the substrate in the cell array region.

5. The three-dimensional semiconductor memory device of claim 1 , wherein the end portions of the gate electrodes in the contact region are substantially equidistant from a plane that includes the upper surface of the substrate in the cell array region.

6. The three-dimensional semiconductor memory device of claim 1 , wherein the substrate further comprises a peripheral circuit region adjacent to the contact region, the contact region disposed between the cell array region and the peripheral circuit region.

7. The three-dimensional semiconductor memory device of claim 6 , further comprising:
a peripheral gate electrode in the peripheral circuit region;
source/drain regions in the substrate at opposite sides of the peripheral gate electrode; and
a peripheral contact plug connected to at least one of the source/drain regions,
wherein a vertical length of the peripheral contact plug is smaller than a vertical length of the stack structure.

8. The three-dimensional semiconductor memory device of claim 1 , wherein the gate electrodes comprise a lowermost gate electrode,
wherein the cell contact plugs comprise a first cell contact plug connected to an end portion of the lowermost gate electrode, and
wherein a vertical length of the first cell contact plug is smaller than a vertical length of the stack structure.

9. The three-dimensional semiconductor memory device of claim 1 , wherein the gate electrodes comprise a lowermost gate electrode, an uppermost gate electrode, and intermediate gate electrodes between the lowermost gate electrode and the uppermost gate electrode,
wherein the cell contact plugs comprise a first cell contact plug connected to the end portion of the lowermost gate electrode and second cell contact plugs connected to the end portions of respective ones of the intermediate gate electrodes, and
wherein a vertical length of the first cell contact plug is substantially equal to vertical lengths of the second cell contact plugs.

10. The three-dimensional semiconductor memory device of claim 1 , wherein the gate electrodes comprise an uppermost gate electrode,
wherein the substrate further comprises a peripheral circuit region, and
wherein the stack structure further comprises an uppermost insulating pattern on the uppermost gate electrode.

11. The three-dimensional semiconductor memory device of claim 10 , further comprising:
an interlayer insulating pattern in the contact region and the peripheral circuit region, an upper surface of the interlayer insulating pattern substantially coplanar with an upper surface of the uppermost insulating pattern,
wherein a vertical length of the stack structure is greater than a height of the interlayer insulating pattern from the upper surface of the substrate in the peripheral circuit region.

12. The three-dimensional semiconductor memory device of claim 1 , wherein the stack structure comprises a plurality of stack structures,
wherein the plurality of stack structures comprise a first stack structure and a second stack structure spaced apart from each other in a first direction,
wherein the first stack structure and the second stack structure comprise the gate electrodes, and
wherein at least two of the gate electrodes adjacent in the first direction and positioned at a same level with respect to the upper surface of the substrate in the contact region are connected to each other by a connection electrode interposed therebetween at the same level.

13. The three-dimensional semiconductor memory device of claim 1 , wherein the gate electrodes extend in a first direction, the gate electrodes comprising pad structures which are constituted by the end portions of the gate electrodes and are vertically stacked on the substrate in the contact region,
wherein the pad structures comprise a first pad and a second pad which are sequentially stacked on the substrate, and
wherein the second pad exposes a portion of an upper surface of the first pad that is adjacent the second pad in a second direction crossing the first direction.

14. A three-dimensional semiconductor memory device comprising:
a substrate comprising a cell array region, a peripheral circuit region, and a contact region between the cell array region and the peripheral circuit region, the substrate in the cell array region and the contact region having an upper surface recessed from an upper surface of the substrate in the peripheral circuit region;
a stack structure comprising gate electrodes sequentially stacked on the substrate in the cell array region and the contact region;
vertical structures penetrating the stack structure; and
cell contact plugs in contact with respective upper surfaces of end portions of the gate electrodes in the contact region,
wherein the upper surfaces of the end portions of the gate electrodes are positioned at a different level from the upper surface of the substrate in the peripheral circuit region,
wherein the cell contact plugs have a substantially same vertical length,
wherein the end portions of the gate electrodes in the contact region are substantially equidistant from a plane that includes the upper surface of the substrate in the cell array region,
wherein the upper surfaces of the end portions of the gate electrodes are sloped with respect to

Assignees

• Shin Joongshik
• Park Jihoon
• Son Yong Hoon
• Woo Jongho
• JUNG Euntaek
• Cha Junho
• Samsung Electronics Co Ltd

Inventors

• Shin Joongshik
• Park Jihoon
• Son Yong-Hoon
• Woo Jongho
• JUNG Euntaek
• Cha Junho

Classifications

• H10P50/73

  using masks for insulating materials · CPC title

• H10P50/694 Primary

  characterised by their behaviour during the process, e.g. soluble masks or redeposited masks · CPC title

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H01L27/11582 Primary

  Electricity · mapped topic

• H01L21/308

  Electricity · mapped topic