Semiconductor device, method for manufacturing the same, method for generating mask data, mask and computer readable recording medium

Patent metadata

Field	Value
Publication number	US-2016358901-A1
Application number	US-201615242885-A
Country	US
Kind code	A1
Filing date	Aug 22, 2016
Priority date	Mar 17, 2000
Publication date	Dec 8, 2016
Grant date	—

Abstract

A semiconductor device has first wiring layers and a plurality of dummy wiring layers that are provided on the same level as the first wiring layers. The semiconductor device defines a row direction, and first virtual linear lines extending in a direction traversing the row direction. The row direction and the first virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the first virtual linear lines. The semiconductor device also defines a column direction perpendicular to the row direction, and second virtual linear lines extending in a direction traversing the column direction. The column direction and the second virtual linear lines define an angle of 2-40 degrees, and the dummy wiring layers are disposed in a manner to be located on the second virtual linear lines.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a plurality of first wiring layers; a plurality of restriction regions each including at least one of said first wiring layers; and a plurality of dummy wiring layers provided in regions other than said restriction regions; wherein each of said dummy wiring layers does not connect with said restriction regions.

2 . The semiconductor device of claim 1 , wherein all of said dummy wiring layers are similarly shaped.

3 . The semiconductor device of claim 1 , wherein all of said dummy wiring layers have a square shape.

4 . The semiconductor device of claim 1 , wherein each of said dummy wiring layers have a width of approximately 2 μm.

5 . The semiconductor device of claim 1 , wherein each of said dummy wiring layers are spaced approximately 1 μm apart.

6 . The semiconductor device of claim 1 , wherein said dummy wiring layers are staggered relative to each other.

Assignees

• Seiko Epson Corp

Inventors

• Mori Katsumi
• Kawahara Kei
• Kasuya Yoshikazu

Classifications

• H10W20/092

  by smoothing the dielectric parts · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/43 Primary

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title